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[4/4] arm64: dts: qcom: sc8280xp: Describe TCSR download mode register

Message ID 20240307-topic-8280_nodes-v1-4-4eba20e08902@linaro.org
State Accepted
Commit 27ef06ebd289992ad4469632b440cd0b072be562
Headers show
Series Random 8280 bits | expand

Commit Message

Konrad Dybcio March 7, 2024, 8:25 p.m. UTC 
To allow for swift EDL reboots, describe the respective register under
the scm node.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 44c8d543eb67..505cae44f828 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -300,6 +300,7 @@  firmware {
 		scm: scm {
 			compatible = "qcom,scm-sc8280xp", "qcom,scm";
 			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
+			qcom,dload-mode = <&tcsr 0x13000>;
 		};
 	};