diff mbox series

dt-bindings: serial: renesas,scif: Document R9A09G057 support

Message ID 20240305171600.328699-1-prabhakar.mahadev-lad.rj@bp.renesas.com
State New
Headers show
Series dt-bindings: serial: renesas,scif: Document R9A09G057 support | expand

Commit Message

Prabhakar March 5, 2024, 5:16 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document support for the Serial Communication Interface with FIFO (SCIF)
available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in
the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
(R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC has
three additional interrupts: one for Tx end/Rx ready and the other two for
Rx and Tx buffer full, which are edge-triggered.

No driver changes are required as generic compatible string
"renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 .../bindings/serial/renesas,scif.yaml         | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Krzysztof Kozlowski March 6, 2024, 7:34 a.m. UTC | #1 
On 05/03/2024 18:16, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document support for the Serial Communication Interface with FIFO (SCIF)
> available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in
> the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
> (R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC has
> three additional interrupts: one for Tx end/Rx ready and the other two for
> Rx and Tx buffer full, which are edge-triggered.
> 
> No driver changes are required as generic compatible string
> "renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
>  .../bindings/serial/renesas,scif.yaml         | 21 +++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> index 4610a5bd580c..b2c2305e352c 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> @@ -80,6 +80,7 @@ properties:
>                - renesas,scif-r9a07g043      # RZ/G2UL and RZ/Five
>                - renesas,scif-r9a07g054      # RZ/V2L
>                - renesas,scif-r9a08g045      # RZ/G3S
> +              - renesas,scif-r9a09g057      # RZ/V2H(P)
>            - const: renesas,scif-r9a07g044   # RZ/G2{L,LC} fallback
>  
>    reg:
> @@ -101,6 +102,16 @@ properties:
>            - description: Break interrupt
>            - description: Data Ready interrupt
>            - description: Transmit End interrupt
> +      - items:
> +          - description: Error interrupt
> +          - description: Receive buffer full interrupt
> +          - description: Transmit buffer empty interrupt
> +          - description: Break interrupt
> +          - description: Data Ready interrupt
> +          - description: Transmit End interrupt
> +          - description: Transmit End/Data Ready interrupt
> +          - description: Receive buffer full interrupt (EDGE trigger)
> +          - description: Transmit buffer empty interrupt (EDGE trigger)

You should narrow the choice per variant. Your patch is now saying that
all devices could have 9 interrupts.

Best regards,
Krzysztof
Prabhakar March 6, 2024, 9:15 a.m. UTC | #2 
Hi Krzysztof,

Thank you for the review.

On Wed, Mar 6, 2024 at 7:34 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/03/2024 18:16, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document support for the Serial Communication Interface with FIFO (SCIF)
> > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in
> > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
> > (R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC has
> > three additional interrupts: one for Tx end/Rx ready and the other two for
> > Rx and Tx buffer full, which are edge-triggered.
> >
> > No driver changes are required as generic compatible string
> > "renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > ---
> >  .../bindings/serial/renesas,scif.yaml         | 21 +++++++++++++++++++
> >  1 file changed, 21 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > index 4610a5bd580c..b2c2305e352c 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > @@ -80,6 +80,7 @@ properties:
> >                - renesas,scif-r9a07g043      # RZ/G2UL and RZ/Five
> >                - renesas,scif-r9a07g054      # RZ/V2L
> >                - renesas,scif-r9a08g045      # RZ/G3S
> > +              - renesas,scif-r9a09g057      # RZ/V2H(P)
> >            - const: renesas,scif-r9a07g044   # RZ/G2{L,LC} fallback
> >
> >    reg:
> > @@ -101,6 +102,16 @@ properties:
> >            - description: Break interrupt
> >            - description: Data Ready interrupt
> >            - description: Transmit End interrupt
> > +      - items:
> > +          - description: Error interrupt
> > +          - description: Receive buffer full interrupt
> > +          - description: Transmit buffer empty interrupt
> > +          - description: Break interrupt
> > +          - description: Data Ready interrupt
> > +          - description: Transmit End interrupt
> > +          - description: Transmit End/Data Ready interrupt
> > +          - description: Receive buffer full interrupt (EDGE trigger)
> > +          - description: Transmit buffer empty interrupt (EDGE trigger)
>
> You should narrow the choice per variant. Your patch is now saying that
> all devices could have 9 interrupts.
>
Ok I will fix the existing binding first and then add support for RZ/V2H SoC.

Cheers,
Prabhakar
Geert Uytterhoeven March 6, 2024, 10:15 a.m. UTC | #3 
Hi Prabhakar,

On Wed, Mar 6, 2024 at 11:06 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Wed, Mar 6, 2024 at 9:53 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Mar 5, 2024 at 6:16 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Document support for the Serial Communication Interface with FIFO (SCIF)
> > > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in
> > > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
> > > (R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC has
> > > three additional interrupts: one for Tx end/Rx ready and the other two for
> > > Rx and Tx buffer full, which are edge-triggered.
> > >
> > > No driver changes are required as generic compatible string
> > > "renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) SoC.
> >
> > If you declare SCIF on RZ/V2H compatible with SCIF on RZ/G2L, you
> > state that the current driver works fine (but perhaps suboptimal),
> > without adding support for the extra 3 interrupts?
> >
> Yes the current driver works without using the extra interrupts on the
> RZ/V2H. The extra interrupts on the RZ/V2H are just sort of duplicate
> ie
> - Transmit End/Data Ready interrupt , for which we we have two
> seperate interrupts already
> - Receive buffer full interrupt (EDGE trigger), for which we already
> have a Level triggered interrupt
> - Transmit buffer empty interrupt (EDGE trigger), for which we already
> have a Level triggered interrupt

Thanks for the confirmation!

> Are you suggesting to not fallback on RZ/G2L and instead make RZ/V2H
> an explicit one so that in future we handle these 3 extra interrupts?

In light of the confirmation above, I am _not_ suggesting that.
I just wanted a clarification: if the current driver would not operate
properly without changes, the fallback would not have been appropriate.
W.r.t. the extra interrupts, you can add support to the driver later,
if/when a need or desire ever arises.

Gr{oetje,eeting}s,

                        Geert
Prabhakar March 7, 2024, 10:08 a.m. UTC | #4 
Hi Geert,

On Wed, Mar 6, 2024 at 10:21 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Geert,
>
> On Wed, Mar 6, 2024 at 10:15 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> >
> > Hi Prabhakar,
> >
> > On Wed, Mar 6, 2024 at 11:06 AM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Wed, Mar 6, 2024 at 9:53 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > On Tue, Mar 5, 2024 at 6:16 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Document support for the Serial Communication Interface with FIFO (SCIF)
> > > > > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in
> > > > > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
> > > > > (R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC has
> > > > > three additional interrupts: one for Tx end/Rx ready and the other two for
> > > > > Rx and Tx buffer full, which are edge-triggered.
> > > > >
> > > > > No driver changes are required as generic compatible string
> > > > > "renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) SoC.
> > > >
> > > > If you declare SCIF on RZ/V2H compatible with SCIF on RZ/G2L, you
> > > > state that the current driver works fine (but perhaps suboptimal),
> > > > without adding support for the extra 3 interrupts?
> > > >
> > > Yes the current driver works without using the extra interrupts on the
> > > RZ/V2H. The extra interrupts on the RZ/V2H are just sort of duplicate
> > > ie
> > > - Transmit End/Data Ready interrupt , for which we we have two
> > > seperate interrupts already
> > > - Receive buffer full interrupt (EDGE trigger), for which we already
> > > have a Level triggered interrupt
> > > - Transmit buffer empty interrupt (EDGE trigger), for which we already
> > > have a Level triggered interrupt
> >
> > Thanks for the confirmation!
> >
> > > Are you suggesting to not fallback on RZ/G2L and instead make RZ/V2H
> > > an explicit one so that in future we handle these 3 extra interrupts?
> >
> > In light of the confirmation above, I am _not_ suggesting that.
> >
With the introduction of validation checks for interrupts, falling
back to "renesas,scif-r9a07g044" for RZ/V2H will be difficult for
validating interrupt count.

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,scif-r7s9210
              - renesas,scif-r9a07g044
    then:
      properties:
        interrupts:
          minItems: 6

        interrupt-names:
          minItems: 6

With the above check RZ/V2H fall into this if block,

Is there any way I can specify to match two compat strings?

Cheers,
Prabhakar
Geert Uytterhoeven March 7, 2024, 10:18 a.m. UTC | #5 
Hi Prabhakar,

On Thu, Mar 7, 2024 at 11:09 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Wed, Mar 6, 2024 at 10:21 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Wed, Mar 6, 2024 at 10:15 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Wed, Mar 6, 2024 at 11:06 AM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > On Wed, Mar 6, 2024 at 9:53 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > On Tue, Mar 5, 2024 at 6:16 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Document support for the Serial Communication Interface with FIFO (SCIF)
> > > > > > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in
> > > > > > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
> > > > > > (R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC has
> > > > > > three additional interrupts: one for Tx end/Rx ready and the other two for
> > > > > > Rx and Tx buffer full, which are edge-triggered.
> > > > > >
> > > > > > No driver changes are required as generic compatible string
> > > > > > "renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) SoC.
> > > > >
> > > > > If you declare SCIF on RZ/V2H compatible with SCIF on RZ/G2L, you
> > > > > state that the current driver works fine (but perhaps suboptimal),
> > > > > without adding support for the extra 3 interrupts?
> > > > >
> > > > Yes the current driver works without using the extra interrupts on the
> > > > RZ/V2H. The extra interrupts on the RZ/V2H are just sort of duplicate
> > > > ie
> > > > - Transmit End/Data Ready interrupt , for which we we have two
> > > > seperate interrupts already
> > > > - Receive buffer full interrupt (EDGE trigger), for which we already
> > > > have a Level triggered interrupt
> > > > - Transmit buffer empty interrupt (EDGE trigger), for which we already
> > > > have a Level triggered interrupt
> > >
> > > Thanks for the confirmation!
> > >
> > > > Are you suggesting to not fallback on RZ/G2L and instead make RZ/V2H
> > > > an explicit one so that in future we handle these 3 extra interrupts?
> > >
> > > In light of the confirmation above, I am _not_ suggesting that.
> > >
> With the introduction of validation checks for interrupts, falling
> back to "renesas,scif-r9a07g044" for RZ/V2H will be difficult for
> validating interrupt count.
>
>   - if:
>       properties:
>         compatible:
>           contains:
>             enum:
>               - renesas,scif-r7s9210
>               - renesas,scif-r9a07g044
>     then:
>       properties:
>         interrupts:
>           minItems: 6
>
>         interrupt-names:
>           minItems: 6
>
> With the above check RZ/V2H fall into this if block,
>
> Is there any way I can specify to match two compat strings?

if r9a09g057 then ... else if r7s9210 || r9a07g044 then ...?

Gr{oetje,eeting}s,

                        Geert
Prabhakar March 7, 2024, 10:55 a.m. UTC | #6 
Hi Geert,

On Thu, Mar 7, 2024 at 10:18 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Mar 7, 2024 at 11:09 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Wed, Mar 6, 2024 at 10:21 AM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Wed, Mar 6, 2024 at 10:15 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > On Wed, Mar 6, 2024 at 11:06 AM Lad, Prabhakar
> > > > <prabhakar.csengg@gmail.com> wrote:
> > > > > On Wed, Mar 6, 2024 at 9:53 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > > On Tue, Mar 5, 2024 at 6:16 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > >
> > > > > > > Document support for the Serial Communication Interface with FIFO (SCIF)
> > > > > > > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in
> > > > > > > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
> > > > > > > (R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC has
> > > > > > > three additional interrupts: one for Tx end/Rx ready and the other two for
> > > > > > > Rx and Tx buffer full, which are edge-triggered.
> > > > > > >
> > > > > > > No driver changes are required as generic compatible string
> > > > > > > "renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) SoC.
> > > > > >
> > > > > > If you declare SCIF on RZ/V2H compatible with SCIF on RZ/G2L, you
> > > > > > state that the current driver works fine (but perhaps suboptimal),
> > > > > > without adding support for the extra 3 interrupts?
> > > > > >
> > > > > Yes the current driver works without using the extra interrupts on the
> > > > > RZ/V2H. The extra interrupts on the RZ/V2H are just sort of duplicate
> > > > > ie
> > > > > - Transmit End/Data Ready interrupt , for which we we have two
> > > > > seperate interrupts already
> > > > > - Receive buffer full interrupt (EDGE trigger), for which we already
> > > > > have a Level triggered interrupt
> > > > > - Transmit buffer empty interrupt (EDGE trigger), for which we already
> > > > > have a Level triggered interrupt
> > > >
> > > > Thanks for the confirmation!
> > > >
> > > > > Are you suggesting to not fallback on RZ/G2L and instead make RZ/V2H
> > > > > an explicit one so that in future we handle these 3 extra interrupts?
> > > >
> > > > In light of the confirmation above, I am _not_ suggesting that.
> > > >
> > With the introduction of validation checks for interrupts, falling
> > back to "renesas,scif-r9a07g044" for RZ/V2H will be difficult for
> > validating interrupt count.
> >
> >   - if:
> >       properties:
> >         compatible:
> >           contains:
> >             enum:
> >               - renesas,scif-r7s9210
> >               - renesas,scif-r9a07g044
> >     then:
> >       properties:
> >         interrupts:
> >           minItems: 6
> >
> >         interrupt-names:
> >           minItems: 6
> >
> > With the above check RZ/V2H fall into this if block,
> >
> > Is there any way I can specify to match two compat strings?
>
> if r9a09g057 then ... else if r7s9210 || r9a07g044 then ...?
>
Thanks for the pointer (I was grepping for elif ;)).

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 4610a5bd580c..b2c2305e352c 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -80,6 +80,7 @@  properties:
               - renesas,scif-r9a07g043      # RZ/G2UL and RZ/Five
               - renesas,scif-r9a07g054      # RZ/V2L
               - renesas,scif-r9a08g045      # RZ/G3S
+              - renesas,scif-r9a09g057      # RZ/V2H(P)
           - const: renesas,scif-r9a07g044   # RZ/G2{L,LC} fallback
 
   reg:
@@ -101,6 +102,16 @@  properties:
           - description: Break interrupt
           - description: Data Ready interrupt
           - description: Transmit End interrupt
+      - items:
+          - description: Error interrupt
+          - description: Receive buffer full interrupt
+          - description: Transmit buffer empty interrupt
+          - description: Break interrupt
+          - description: Data Ready interrupt
+          - description: Transmit End interrupt
+          - description: Transmit End/Data Ready interrupt
+          - description: Receive buffer full interrupt (EDGE trigger)
+          - description: Transmit buffer empty interrupt (EDGE trigger)
 
   interrupt-names:
     oneOf:
@@ -116,6 +127,16 @@  properties:
           - const: bri
           - const: dri
           - const: tei
+      - items:
+          - const: eri
+          - const: rxi
+          - const: txi
+          - const: bri
+          - const: dri
+          - const: tei
+          - const: teidri
+          - const: rxi-edge
+          - const: txi-edge
 
   clocks:
     minItems: 1