[33/41] target/sparc: Add feature bit for VIS4

Message ID	20240302051601.53649-34-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 33/41] target/sparc: Add feature bit for VIS4 Date: Fri, 1 Mar 2024 19:15:53 -1000 Message-Id: <20240302051601.53649-34-richard.henderson@linaro.org> In-Reply-To: <20240302051601.53649-1-richard.henderson@linaro.org> References: <20240302051601.53649-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/sparc: Implement VIS4 \| expand [00/41] target/sparc: Implement VIS4 [01/41] linux-user/sparc: Add more hwcap bits for sparc64 [02/41] target/sparc: Fix FEXPAND [03/41] target/sparc: Fix FMUL8x16 [04/41] target/sparc: Fix FMUL8x16A{U,L} [05/41] target/sparc: Fix FMULD8*X16 [06/41] target/sparc: Fix FPMERGE [07/41] target/sparc: Split out do_ms16b [08/41] target/sparc: Perform DFPREG/QFPREG in decodetree [09/41] target/sparc: Remove gen_dest_fpr_D [10/41] target/sparc: Remove cpu_fpr[] [11/41] target/sparc: Use gvec for VIS1 parallel add/sub [12/41] target/sparc: Implement FMAf extension [13/41] target/sparc: Add feature bits for VIS 3 [14/41] target/sparc: Implement ADDXC, ADDXCcc [15/41] target/sparc: Implement CMASK instructions [16/41] target/sparc: Implement FCHKSM16 [17/41] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD [18/41] target/sparc: Implement FNMUL [19/41] target/sparc: Implement FLCMP [20/41] target/sparc: Implement FMEAN16 [21/41] target/sparc: Implement FPADD64 FPSUB64 [22/41] target/sparc: Implement FPADDS, FPSUBS [23/41] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 [24/41] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS [25/41] target/sparc: Implement LDXEFSR [26/41] target/sparc: Implement LZCNT [27/41] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd [28/41] target/sparc: Implement PDISTN [29/41] target/sparc: Implement UMULXHI [30/41] target/sparc: Implement XMULX [31/41] target/sparc: Enable VIS3 feature bit [32/41] target/sparc: Implement IMA extension [33/41] target/sparc: Add feature bit for VIS4 [34/41] target/sparc: Implement FALIGNDATAi [35/41] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS [36/41] target/sparc: Implement VIS4 comparisons [37/41] target/sparc: Implement FPMIN, FPMAX [38/41] target/sparc: Implement SUBXC, SUBXCcc [39/41] target/sparc: Implement MWAIT [40/41] target/sparc: Implement monitor asis [41/41] target/sparc: Enable VIS4 feature bit

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20240302051601.53649-34-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
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	atar4qemu@gmail.com
Subject: [PATCH 33/41] target/sparc: Add feature bit for VIS4
Date: Fri,  1 Mar 2024 19:15:53 -1000
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Series

target/sparc: Implement VIS4 | expand

Comments

Philippe Mathieu-Daudé May 10, 2024, 5:05 p.m. UTC | #1

On 2/3/24 06:15, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/sparc/translate.c       | 2 ++
>   target/sparc/cpu-feature.h.inc | 1 +
>   2 files changed, 3 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 56ee3927af..77b53cbf3b 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2402,6 +2402,7 @@  static int extract_qfpreg(DisasContext *dc, int x)
 # define avail_VIS2(C)    ((C)->def->features & CPU_FEATURE_VIS2)
 # define avail_VIS3(C)    ((C)->def->features & CPU_FEATURE_VIS3)
 # define avail_VIS3B(C)   avail_VIS3(C)
+# define avail_VIS4(C)    ((C)->def->features & CPU_FEATURE_VIS4)
 #else
 # define avail_32(C)      true
 # define avail_ASR17(C)   ((C)->def->features & CPU_FEATURE_ASR17)
@@ -2418,6 +2419,7 @@  static int extract_qfpreg(DisasContext *dc, int x)
 # define avail_VIS2(C)    false
 # define avail_VIS3(C)    false
 # define avail_VIS3B(C)   false
+# define avail_VIS4(C)    false
 #endif
 
 /* Default case for non jump instructions. */
diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc
index e2e6de9144..be81005237 100644
--- a/target/sparc/cpu-feature.h.inc
+++ b/target/sparc/cpu-feature.h.inc
@@ -15,3 +15,4 @@  FEATURE(CASA)
 FEATURE(FMAF)
 FEATURE(VIS3)
 FEATURE(IMA)
+FEATURE(VIS4)

[33/41] target/sparc: Add feature bit for VIS4

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