| Message ID | 20240229010130.1380926-2-atishp@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest | expand |
On 29/02/2024 02:01, Atish Patra wrote: > The counter overflow CSR name is "scountovf" not "sscountovf". > > Fix the csr name. > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Anup Patel <anup@brainfault.org> > Signed-off-by: Atish Patra <atishp@rivosinc.com> > --- > arch/riscv/include/asm/csr.h | 2 +- > arch/riscv/include/asm/errata_list.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 510014051f5d..603e5a3c61f9 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -281,7 +281,7 @@ > #define CSR_HPMCOUNTER30H 0xc9e > #define CSR_HPMCOUNTER31H 0xc9f > > -#define CSR_SSCOUNTOVF 0xda0 > +#define CSR_SCOUNTOVF 0xda0 > > #define CSR_SSTATUS 0x100 > #define CSR_SIE 0x104 > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index ea33288f8a25..cd49eb025ddf 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -114,7 +114,7 @@ asm volatile(ALTERNATIVE( \ > > #define ALT_SBI_PMU_OVERFLOW(__ovl) \ > asm volatile(ALTERNATIVE( \ > - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ > + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ > "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ > THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ > CONFIG_ERRATA_THEAD_PMU) \ Reviewed-by: Clément Léger <cleger@rivosinc.com> Thanks, Clément
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..603e5a3c61f9 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index ea33288f8a25..cd49eb025ddf 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -114,7 +114,7 @@ asm volatile(ALTERNATIVE( \ #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU) \
The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/csr.h | 2 +- arch/riscv/include/asm/errata_list.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)