| Message ID | 20240226-dw-hdma-v3-3-cfcb8171fc24@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: dwc: Add support for integrating HDMA with DWC EP driver | expand |
On Mon, Feb 26, 2024 at 11:30:13AM -0500, Frank Li wrote: > On Mon, Feb 26, 2024 at 05:07:28PM +0530, Manivannan Sadhasivam wrote: > > Instead of maintaining a separate capability for glue drivers that cannot > > support auto detection of the eDMA mapping format, let's pass the mapping > > format directly from them. > > Sorry, what's mapping? is it register address layout? > Memory map containing the register layout for iATU, DMA etc... - Mani > Frank > > > > > This will simplify the code and also allow adding HDMA support that also > > doesn't support auto detection of mapping format. > > > > Suggested-by: Serge Semin <fancer.lancer@gmail.com> > > Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++------- > > drivers/pci/controller/dwc/pcie-designware.h | 5 ++--- > > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- > > 3 files changed, 12 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index ce273c3c5421..3e90b9947a13 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -894,18 +894,20 @@ static int dw_pcie_edma_find_mf(struct dw_pcie *pci) > > { > > u32 val; > > > > + /* > > + * Bail out finding the mapping format if it is already set by the glue > > + * driver. Also ensure that the edma.reg_base is pointing to a valid > > + * memory region. > > + */ > > + if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) > > + return pci->edma.reg_base ? 0 : -ENODEV; > > + > > /* > > * Indirect eDMA CSRs access has been completely removed since v5.40a > > * thus no space is now reserved for the eDMA channels viewport and > > * former DMA CTRL register is no longer fixed to FFs. > > - * > > - * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason > > - * have zeros in the eDMA CTRL register even though the HW-manual > > - * explicitly states there must FFs if the unrolled mapping is enabled. > > - * For such cases the low-level drivers are supposed to manually > > - * activate the unrolled mapping to bypass the auto-detection procedure. > > */ > > - if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) > > + if (dw_pcie_ver_is_ge(pci, 540A)) > > val = 0xFFFFFFFF; > > else > > val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > index 26dae4837462..995805279021 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > @@ -51,9 +51,8 @@ > > > > /* DWC PCIe controller capabilities */ > > #define DW_PCIE_CAP_REQ_RES 0 > > -#define DW_PCIE_CAP_EDMA_UNROLL 1 > > -#define DW_PCIE_CAP_IATU_UNROLL 2 > > -#define DW_PCIE_CAP_CDM_CHECK 3 > > +#define DW_PCIE_CAP_IATU_UNROLL 1 > > +#define DW_PCIE_CAP_CDM_CHECK 2 > > > > #define dw_pcie_cap_is(_pci, _cap) \ > > test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c > > index e9166619b1f9..3c535ef5ea91 100644 > > --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c > > @@ -255,7 +255,7 @@ static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev) > > rcar->dw.ops = &dw_pcie_ops; > > rcar->dw.dev = dev; > > rcar->pdev = pdev; > > - dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL); > > + rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL; > > dw_pcie_cap_set(&rcar->dw, REQ_RES); > > platform_set_drvdata(pdev, rcar); > > > > > > -- > > 2.25.1 > >
On Tue, Feb 27, 2024 at 01:15:33PM +0530, Manivannan Sadhasivam wrote: > On Mon, Feb 26, 2024 at 11:30:13AM -0500, Frank Li wrote: > > On Mon, Feb 26, 2024 at 05:07:28PM +0530, Manivannan Sadhasivam wrote: > > > Instead of maintaining a separate capability for glue drivers that cannot > > > support auto detection of the eDMA mapping format, let's pass the mapping > > > format directly from them. > > > > Sorry, what's mapping? is it register address layout? > > > > Memory map containing the register layout for iATU, DMA etc... the world 'map' is too general. can you use 'register map' at least at one place? There are bunch 'map' related DMA, such iommu map, stream id map, memory page map. The reader need go though whole thread to figure out it is register map. Frank > > - Mani > > > Frank > > > > > > > > This will simplify the code and also allow adding HDMA support that also > > > doesn't support auto detection of mapping format. > > > > > > Suggested-by: Serge Semin <fancer.lancer@gmail.com> > > > Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > --- > > > drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++------- > > > drivers/pci/controller/dwc/pcie-designware.h | 5 ++--- > > > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- > > > 3 files changed, 12 insertions(+), 11 deletions(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > > index ce273c3c5421..3e90b9947a13 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > > @@ -894,18 +894,20 @@ static int dw_pcie_edma_find_mf(struct dw_pcie *pci) > > > { > > > u32 val; > > > > > > + /* > > > + * Bail out finding the mapping format if it is already set by the glue > > > + * driver. Also ensure that the edma.reg_base is pointing to a valid > > > + * memory region. > > > + */ > > > + if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) > > > + return pci->edma.reg_base ? 0 : -ENODEV; > > > + > > > /* > > > * Indirect eDMA CSRs access has been completely removed since v5.40a > > > * thus no space is now reserved for the eDMA channels viewport and > > > * former DMA CTRL register is no longer fixed to FFs. > > > - * > > > - * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason > > > - * have zeros in the eDMA CTRL register even though the HW-manual > > > - * explicitly states there must FFs if the unrolled mapping is enabled. > > > - * For such cases the low-level drivers are supposed to manually > > > - * activate the unrolled mapping to bypass the auto-detection procedure. > > > */ > > > - if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) > > > + if (dw_pcie_ver_is_ge(pci, 540A)) > > > val = 0xFFFFFFFF; > > > else > > > val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > > index 26dae4837462..995805279021 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > > @@ -51,9 +51,8 @@ > > > > > > /* DWC PCIe controller capabilities */ > > > #define DW_PCIE_CAP_REQ_RES 0 > > > -#define DW_PCIE_CAP_EDMA_UNROLL 1 > > > -#define DW_PCIE_CAP_IATU_UNROLL 2 > > > -#define DW_PCIE_CAP_CDM_CHECK 3 > > > +#define DW_PCIE_CAP_IATU_UNROLL 1 > > > +#define DW_PCIE_CAP_CDM_CHECK 2 > > > > > > #define dw_pcie_cap_is(_pci, _cap) \ > > > test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) > > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c > > > index e9166619b1f9..3c535ef5ea91 100644 > > > --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c > > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c > > > @@ -255,7 +255,7 @@ static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev) > > > rcar->dw.ops = &dw_pcie_ops; > > > rcar->dw.dev = dev; > > > rcar->pdev = pdev; > > > - dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL); > > > + rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL; > > > dw_pcie_cap_set(&rcar->dw, REQ_RES); > > > platform_set_drvdata(pdev, rcar); > > > > > > > > > -- > > > 2.25.1 > > > > > -- > மணிவண்ணன் சதாசிவம்
On Tue, Feb 27, 2024 at 12:38:52PM -0500, Frank Li wrote: > On Tue, Feb 27, 2024 at 01:15:33PM +0530, Manivannan Sadhasivam wrote: > > On Mon, Feb 26, 2024 at 11:30:13AM -0500, Frank Li wrote: > > > On Mon, Feb 26, 2024 at 05:07:28PM +0530, Manivannan Sadhasivam wrote: > > > > Instead of maintaining a separate capability for glue drivers that cannot > > > > support auto detection of the eDMA mapping format, let's pass the mapping > > > > format directly from them. > > > > > > Sorry, what's mapping? is it register address layout? > > > > > > > Memory map containing the register layout for iATU, DMA etc... > > the world 'map' is too general. can you use 'register map' at least at one > place? There are bunch 'map' related DMA, such iommu map, stream id map, > memory page map. The reader need go though whole thread to figure out it is > register map. > This is what used from the start and also what "mf" corresponds to. So I had to use the same terminology. - Mani
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index ce273c3c5421..3e90b9947a13 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -894,18 +894,20 @@ static int dw_pcie_edma_find_mf(struct dw_pcie *pci) { u32 val; + /* + * Bail out finding the mapping format if it is already set by the glue + * driver. Also ensure that the edma.reg_base is pointing to a valid + * memory region. + */ + if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) + return pci->edma.reg_base ? 0 : -ENODEV; + /* * Indirect eDMA CSRs access has been completely removed since v5.40a * thus no space is now reserved for the eDMA channels viewport and * former DMA CTRL register is no longer fixed to FFs. - * - * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason - * have zeros in the eDMA CTRL register even though the HW-manual - * explicitly states there must FFs if the unrolled mapping is enabled. - * For such cases the low-level drivers are supposed to manually - * activate the unrolled mapping to bypass the auto-detection procedure. */ - if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) + if (dw_pcie_ver_is_ge(pci, 540A)) val = 0xFFFFFFFF; else val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 26dae4837462..995805279021 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -51,9 +51,8 @@ /* DWC PCIe controller capabilities */ #define DW_PCIE_CAP_REQ_RES 0 -#define DW_PCIE_CAP_EDMA_UNROLL 1 -#define DW_PCIE_CAP_IATU_UNROLL 2 -#define DW_PCIE_CAP_CDM_CHECK 3 +#define DW_PCIE_CAP_IATU_UNROLL 1 +#define DW_PCIE_CAP_CDM_CHECK 2 #define dw_pcie_cap_is(_pci, _cap) \ test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c index e9166619b1f9..3c535ef5ea91 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -255,7 +255,7 @@ static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev) rcar->dw.ops = &dw_pcie_ops; rcar->dw.dev = dev; rcar->pdev = pdev; - dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL); + rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL; dw_pcie_cap_set(&rcar->dw, REQ_RES); platform_set_drvdata(pdev, rcar);