| Message ID | 13deb8c5cb58e08c1b47decd112b51e8e0b6c4dc.1707677804.git.mehdi.djait.k@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [RESEND,v13,1/3] media: dt-bindings: media: add bindings for Rockchip CIF | expand |
Hi Mehdi, Thanks for the patchset. On Sun, Feb 11, 2024 at 08:03:30PM +0100, Mehdi Djait wrote: > From: Mehdi Djait <mehdi.djait@bootlin.com> > > Add a documentation for the Rockchip Camera Interface binding. > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net> > Signed-off-by: Mehdi Djait <mehdi.djait@bootlin.com> > Signed-off-by: Mehdi Djait <mehdi.djait.k@gmail.com> > --- > .../bindings/media/rockchip,px30-vip.yaml | 123 ++++++++++++++++++ > 1 file changed, 123 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > new file mode 100644 > index 000000000000..6af4a9b6774a > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > @@ -0,0 +1,123 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip Camera Interface (CIF) > + > +maintainers: > + - Mehdi Djait <mehdi.djait@bootlin.com> > + > +description: > + CIF is a camera interface present on some Rockchip SoCs. It receives the data > + from Camera sensor or CCIR656 encoder and transfers it into system main memory > + by AXI bus. > + > +properties: > + compatible: > + const: rockchip,px30-vip > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: ACLK > + - description: HCLK > + - description: PCLK > + > + clock-names: > + items: > + - const: aclk > + - const: hclk > + - const: pclk > + > + resets: > + items: > + - description: AXI > + - description: AHB > + - description: PCLK IN > + > + reset-names: > + items: > + - const: axi > + - const: ahb > + - const: pclkin > + > + power-domains: > + maxItems: 1 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: input port on the parallel interface > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + bus-type: > + enum: [5, 6] > + > + required: > + - bus-type What about the vsync-active, hsync-active and data-active properties? Aren't they relevant for this device? Are there default values? This should be part of the bindings for the device, shouldn't it? > + > + required: > + - port@0 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/px30-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/media/video-interfaces.h> > + #include <dt-bindings/power/px30-power.h> > + > + parent { > + #address-cells = <2>; > + #size-cells = <2>; > + > + video-capture@ff490000 { > + compatible = "rockchip,px30-vip"; > + reg = <0x0 0xff490000 0x0 0x200>; > + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; > + clock-names = "aclk", "hclk", "pclk"; > + power-domains = <&power PX30_PD_VI>; > + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; > + reset-names = "axi", "ahb", "pclkin"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + cif_in: endpoint { > + remote-endpoint = <&tw9900_out>; > + bus-type = <MEDIA_BUS_TYPE_BT656>; > + }; > + }; > + }; > + }; > + }; > +...
Hi Sakari, Thank you for the review. On Tue, Feb 13, 2024 at 12:04:58PM +0000, Sakari Ailus wrote: > Hi Mehdi, > > Thanks for the patchset. > > On Sun, Feb 11, 2024 at 08:03:30PM +0100, Mehdi Djait wrote: > > From: Mehdi Djait <mehdi.djait@bootlin.com> > > > > Add a documentation for the Rockchip Camera Interface binding. > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net> > > Signed-off-by: Mehdi Djait <mehdi.djait@bootlin.com> > > Signed-off-by: Mehdi Djait <mehdi.djait.k@gmail.com> > > --- > > .../bindings/media/rockchip,px30-vip.yaml | 123 ++++++++++++++++++ > > 1 file changed, 123 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > new file mode 100644 > > index 000000000000..6af4a9b6774a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > @@ -0,0 +1,123 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Rockchip Camera Interface (CIF) > > + > > +maintainers: > > + - Mehdi Djait <mehdi.djait@bootlin.com> > > + > > +description: > > + CIF is a camera interface present on some Rockchip SoCs. It receives the data > > + from Camera sensor or CCIR656 encoder and transfers it into system main memory > > + by AXI bus. > > + > > +properties: > > + compatible: > > + const: rockchip,px30-vip > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: ACLK > > + - description: HCLK > > + - description: PCLK > > + > > + clock-names: > > + items: > > + - const: aclk > > + - const: hclk > > + - const: pclk > > + > > + resets: > > + items: > > + - description: AXI > > + - description: AHB > > + - description: PCLK IN > > + > > + reset-names: > > + items: > > + - const: axi > > + - const: ahb > > + - const: pclkin > > + > > + power-domains: > > + maxItems: 1 > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: input port on the parallel interface > > + > > + properties: > > + endpoint: > > + $ref: video-interfaces.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + bus-type: > > + enum: [5, 6] > > + > > + required: > > + - bus-type > > What about the vsync-active, hsync-active and data-active properties? > Aren't they relevant for this device? Are there default values? This should > be part of the bindings for the device, shouldn't it? >
Hi Mehdi, On Tue, Feb 20, 2024 at 06:04:10PM +0100, Mehdi Djait wrote: > Hi Sakari, > > Thank you for the review. You're welcome! > > On Tue, Feb 13, 2024 at 12:04:58PM +0000, Sakari Ailus wrote: > > Hi Mehdi, > > > > Thanks for the patchset. > > > > On Sun, Feb 11, 2024 at 08:03:30PM +0100, Mehdi Djait wrote: > > > From: Mehdi Djait <mehdi.djait@bootlin.com> > > > > > > Add a documentation for the Rockchip Camera Interface binding. > > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > > Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net> > > > Signed-off-by: Mehdi Djait <mehdi.djait@bootlin.com> > > > Signed-off-by: Mehdi Djait <mehdi.djait.k@gmail.com> > > > --- > > > .../bindings/media/rockchip,px30-vip.yaml | 123 ++++++++++++++++++ > > > 1 file changed, 123 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > new file mode 100644 > > > index 000000000000..6af4a9b6774a > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > @@ -0,0 +1,123 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Rockchip Camera Interface (CIF) > > > + > > > +maintainers: > > > + - Mehdi Djait <mehdi.djait@bootlin.com> > > > + > > > +description: > > > + CIF is a camera interface present on some Rockchip SoCs. It receives the data > > > + from Camera sensor or CCIR656 encoder and transfers it into system main memory > > > + by AXI bus. > > > + > > > +properties: > > > + compatible: > > > + const: rockchip,px30-vip > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + clocks: > > > + items: > > > + - description: ACLK > > > + - description: HCLK > > > + - description: PCLK > > > + > > > + clock-names: > > > + items: > > > + - const: aclk > > > + - const: hclk > > > + - const: pclk > > > + > > > + resets: > > > + items: > > > + - description: AXI > > > + - description: AHB > > > + - description: PCLK IN > > > + > > > + reset-names: > > > + items: > > > + - const: axi > > > + - const: ahb > > > + - const: pclkin > > > + > > > + power-domains: > > > + maxItems: 1 > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/$defs/port-base > > > + unevaluatedProperties: false > > > + description: input port on the parallel interface > > > + > > > + properties: > > > + endpoint: > > > + $ref: video-interfaces.yaml# > > > + unevaluatedProperties: false > > > + > > > + properties: > > > + bus-type: > > > + enum: [5, 6] > > > + > > > + required: > > > + - bus-type > > > > What about the vsync-active, hsync-active and data-active properties? > > Aren't they relevant for this device? Are there default values? This should > > be part of the bindings for the device, shouldn't it? > > > > From what I gathered from the Rockchip PX30 TRM and the other > available documents from Rockchip, I will add the following: > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > index 6af4a9b6774a..6920b0cb0507 100644 > --- a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > @@ -69,6 +69,14 @@ properties: > bus-type: > enum: [5, 6] > > + hsync-active: > + enum: [0, 1] > + default: 1 > + > + vsync-active: > + enum: [0, 1] > + default: 0 I'd use the same default for both, whether it's 0 or 1. > + > > @dt-maintainers, @Conor does this warrant a drop of the reviewed-by tags > in the V14 ? >
Hi Sakari, On Tue, Feb 20, 2024 at 07:30:53PM +0000, Sakari Ailus wrote: > Hi Mehdi, > > On Tue, Feb 20, 2024 at 06:04:10PM +0100, Mehdi Djait wrote: > > Hi Sakari, > > > > Thank you for the review. > > You're welcome! > > > > > On Tue, Feb 13, 2024 at 12:04:58PM +0000, Sakari Ailus wrote: > > > Hi Mehdi, > > > > > > Thanks for the patchset. > > > > > > On Sun, Feb 11, 2024 at 08:03:30PM +0100, Mehdi Djait wrote: > > > > From: Mehdi Djait <mehdi.djait@bootlin.com> > > > > > > > > Add a documentation for the Rockchip Camera Interface binding. > > > > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > > > Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net> > > > > Signed-off-by: Mehdi Djait <mehdi.djait@bootlin.com> > > > > Signed-off-by: Mehdi Djait <mehdi.djait.k@gmail.com> > > > > --- > > > > .../bindings/media/rockchip,px30-vip.yaml | 123 ++++++++++++++++++ > > > > 1 file changed, 123 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > > new file mode 100644 > > > > index 000000000000..6af4a9b6774a > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > > @@ -0,0 +1,123 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Rockchip Camera Interface (CIF) > > > > + > > > > +maintainers: > > > > + - Mehdi Djait <mehdi.djait@bootlin.com> > > > > + > > > > +description: > > > > + CIF is a camera interface present on some Rockchip SoCs. It receives the data > > > > + from Camera sensor or CCIR656 encoder and transfers it into system main memory > > > > + by AXI bus. > > > > + > > > > +properties: > > > > + compatible: > > > > + const: rockchip,px30-vip > > > > + > > > > + reg: > > > > + maxItems: 1 > > > > + > > > > + interrupts: > > > > + maxItems: 1 > > > > + > > > > + clocks: > > > > + items: > > > > + - description: ACLK > > > > + - description: HCLK > > > > + - description: PCLK > > > > + > > > > + clock-names: > > > > + items: > > > > + - const: aclk > > > > + - const: hclk > > > > + - const: pclk > > > > + > > > > + resets: > > > > + items: > > > > + - description: AXI > > > > + - description: AHB > > > > + - description: PCLK IN > > > > + > > > > + reset-names: > > > > + items: > > > > + - const: axi > > > > + - const: ahb > > > > + - const: pclkin > > > > + > > > > + power-domains: > > > > + maxItems: 1 > > > > + > > > > + ports: > > > > + $ref: /schemas/graph.yaml#/properties/ports > > > > + > > > > + properties: > > > > + port@0: > > > > + $ref: /schemas/graph.yaml#/$defs/port-base > > > > + unevaluatedProperties: false > > > > + description: input port on the parallel interface > > > > + > > > > + properties: > > > > + endpoint: > > > > + $ref: video-interfaces.yaml# > > > > + unevaluatedProperties: false > > > > + > > > > + properties: > > > > + bus-type: > > > > + enum: [5, 6] > > > > + > > > > + required: > > > > + - bus-type > > > > > > What about the vsync-active, hsync-active and data-active properties? > > > Aren't they relevant for this device? Are there default values? This should > > > be part of the bindings for the device, shouldn't it? > > > > > > > From what I gathered from the Rockchip PX30 TRM and the other > > available documents from Rockchip, I will add the following: > > > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > index 6af4a9b6774a..6920b0cb0507 100644 > > --- a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > @@ -69,6 +69,14 @@ properties: > > bus-type: > > enum: [5, 6] > > > > + hsync-active: > > + enum: [0, 1] > > + default: 1 > > + > > + vsync-active: > > + enum: [0, 1] > > + default: 0 > > I'd use the same default for both, whether it's 0 or 1. > Is this supposed to be the default value HIGH or LOW if it is not configured by the driver ? because the manual states the following: HREF_POL Href input polarity: 1'b0 : high active 1'b1 : low active RESET VALUE: 0x0 VSYNC_POL Vsync input polarity: 1'b0 : low active 1'b1 : high active RESET VALUE: 0x0 And that's why I chose 1 for hsync and 0 for vsync -- Kind Regards Mehdi Djait
diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml new file mode 100644 index 000000000000..6af4a9b6774a --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Camera Interface (CIF) + +maintainers: + - Mehdi Djait <mehdi.djait@bootlin.com> + +description: + CIF is a camera interface present on some Rockchip SoCs. It receives the data + from Camera sensor or CCIR656 encoder and transfers it into system main memory + by AXI bus. + +properties: + compatible: + const: rockchip,px30-vip + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ACLK + - description: HCLK + - description: PCLK + + clock-names: + items: + - const: aclk + - const: hclk + - const: pclk + + resets: + items: + - description: AXI + - description: AHB + - description: PCLK IN + + reset-names: + items: + - const: axi + - const: ahb + - const: pclkin + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: input port on the parallel interface + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-type: + enum: [5, 6] + + required: + - bus-type + + required: + - port@0 + +required: + - compatible + - reg + - interrupts + - clocks + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/px30-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/media/video-interfaces.h> + #include <dt-bindings/power/px30-power.h> + + parent { + #address-cells = <2>; + #size-cells = <2>; + + video-capture@ff490000 { + compatible = "rockchip,px30-vip"; + reg = <0x0 0xff490000 0x0 0x200>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; + clock-names = "aclk", "hclk", "pclk"; + power-domains = <&power PX30_PD_VI>; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names = "axi", "ahb", "pclkin"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + cif_in: endpoint { + remote-endpoint = <&tw9900_out>; + bus-type = <MEDIA_BUS_TYPE_BT656>; + }; + }; + }; + }; + }; +...