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[5/8] arm64: dts: qcom: msm8996: add second UFS RX lane on MSM8996 platform

Message ID 20240209-msm8996-fix-ufs-v1-5-107b52e57420@linaro.org
State New
Headers show
Series scsi: ufs: qcom: fix UFSDHCD support on MSM8996 platform | expand

Commit Message

Dmitry Baryshkov Feb. 9, 2024, 9:50 p.m. UTC 
Describe the second RX lane used by the UFS controller on MSM8996
platform.

Fixes: 462c5c0aa798 ("dt-bindings: ufs: qcom,ufs: convert to dtschema")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 401c6cce9fec..4472bbc7f058 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2057,7 +2057,8 @@  ufshc: ufshc@624000 {
 				"core_clk_ice",
 				"ref_clk",
 				"tx_lane0_sync_clk",
-				"rx_lane0_sync_clk";
+				"rx_lane0_sync_clk",
+				"rx_lane1_sync_clk";
 			clocks =
 				<&gcc UFS_AXI_CLK_SRC>,
 				<&gcc GCC_UFS_AXI_CLK>,
@@ -2069,7 +2070,8 @@  ufshc: ufshc@624000 {
 				<&gcc GCC_UFS_ICE_CORE_CLK>,
 				<&rpmcc RPM_SMD_LN_BB_CLK>,
 				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
-				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
+				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
+				<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
 			freq-table-hz =
 				<100000000 200000000>,
 				<100000000 200000000>,
@@ -2081,6 +2083,7 @@  ufshc: ufshc@624000 {
 				<0 0>,
 				<0 0>,
 				<0 0>,
+				<0 0>,
 				<0 0>;
 
 			interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,