| Message ID | 20240206145721.2418893-4-msp@baylibre.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] dt-bindings: cpufreq: Add nvmem-cells for chip information | expand |
On 06/02/2024 15:57, Markus Schneider-Pargmann wrote: > Use nvmem cells referring to chip variant and speed grade for the > operating points. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > --- > arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi > index 4193c2b3eed6..d60e1be9eb89 100644 > --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi > @@ -105,6 +105,8 @@ a53_opp_table: opp-table { > compatible = "operating-points-v2-ti-cpu"; > opp-shared; > syscon = <&wkup_conf>; > + nvmem-cells = <&chip_variant>, <&chip_speed>; > + nvmem-cell-names = "chipvariant", "chipspeed"; It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index 4193c2b3eed6..d60e1be9eb89 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -105,6 +105,8 @@ a53_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; opp-shared; syscon = <&wkup_conf>; + nvmem-cells = <&chip_variant>, <&chip_speed>; + nvmem-cell-names = "chipvariant", "chipspeed"; opp-200000000 { opp-hz = /bits/ 64 <200000000>;
Use nvmem cells referring to chip variant and speed grade for the operating points. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 ++ 1 file changed, 2 insertions(+)