| Message ID | 20240125134304.1470404-1-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set | expand |
On 1/25/24 23:43, Peter Maydell wrote: > In kernel commit 5d5b4e8c2d9ec ("arm64/sve: Report FEAT_SVE_B16B16 to > userspace") Linux added ID_AA64ZFR0_el1.B16B16 to the set of ID > register fields which it exposes to userspace. Update our > exported_bits mask to include this. > > (This doesn't yet change any behaviour for us, because we don't yet > have any CPUs that implement this feature, which is part of SVE2.) > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > This is a loose end from last year: in commit 5f7b71fb99dc I > updated our mask values to match the kernel, and when I was > doing that I noticed that the kernel had forgotten to add > B16B16 to its report-to-userspace list when adding support > for that architectural feature. Now the kernel has fixed its > side, we can update again to match it. > --- > target/arm/helper.c | 1 + > tests/tcg/aarch64/sysregs.c | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/helper.c b/target/arm/helper.c index e068d353831..24c0f80679d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8895,6 +8895,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) R_ID_AA64ZFR0_AES_MASK | R_ID_AA64ZFR0_BITPERM_MASK | R_ID_AA64ZFR0_BFLOAT16_MASK | + R_ID_AA64ZFR0_B16B16_MASK | R_ID_AA64ZFR0_SHA3_MASK | R_ID_AA64ZFR0_SM4_MASK | R_ID_AA64ZFR0_I8MM_MASK | diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c index f7a055f1d5f..301e61d0dd4 100644 --- a/tests/tcg/aarch64/sysregs.c +++ b/tests/tcg/aarch64/sysregs.c @@ -137,7 +137,7 @@ int main(void) /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */ get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006)); get_cpu_reg_check_zero(id_aa64dfr1_el1); - get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1, _m(0ff0,ff0f,00ff,00ff)); + get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1, _m(0ff0,ff0f,0fff,00ff)); get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(8ff1,fcff,0000,0000)); get_cpu_reg_check_zero(id_aa64afr0_el1);
In kernel commit 5d5b4e8c2d9ec ("arm64/sve: Report FEAT_SVE_B16B16 to userspace") Linux added ID_AA64ZFR0_el1.B16B16 to the set of ID register fields which it exposes to userspace. Update our exported_bits mask to include this. (This doesn't yet change any behaviour for us, because we don't yet have any CPUs that implement this feature, which is part of SVE2.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- This is a loose end from last year: in commit 5f7b71fb99dc I updated our mask values to match the kernel, and when I was doing that I noticed that the kernel had forgotten to add B16B16 to its report-to-userspace list when adding support for that architectural feature. Now the kernel has fixed its side, we can update again to match it. --- target/arm/helper.c | 1 + tests/tcg/aarch64/sysregs.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)