Message ID | 20240123-x1e80100-dts-missing-nodes-v4-1-072dc2f5c153@linaro.org |
---|---|
State | Superseded |
Headers | show
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Tue, 23 Jan 2024 03:01:53 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id fg7-20020a056402548700b005593c83bdafsm11430074edb.45.2024.01.23.03.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 03:01:53 -0800 (PST) From: Abel Vesa <abel.vesa@linaro.org> Date: Tue, 23 Jan 2024 13:01:15 +0200 Subject: [PATCH v4 01/11] arm64: dts: qcom: x1e80100: Add IPCC node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240123-x1e80100-dts-missing-nodes-v4-1-072dc2f5c153@linaro.org> References: <20240123-x1e80100-dts-missing-nodes-v4-0-072dc2f5c153@linaro.org> In-Reply-To: <20240123-x1e80100-dts-missing-nodes-v4-0-072dc2f5c153@linaro.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Sibi Sankar <quic_sibis@quicinc.com>, Rajendra Nayak <quic_rjendra@quicinc.com> Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa <abel.vesa@linaro.org> X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Series |
[v4,01/11] arm64: dts: qcom: x1e80100: Add IPCC node
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diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 6f75fc342ceb..954f2bd9b1de 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -691,6 +691,17 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + ipcc: mailbox@408000 { + compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00800000 0 0x60000>;