| Message ID | 20240119225257.403222-1-nmorrisson@phytec.com |
|---|---|
| State | Accepted |
| Commit | f4ee6882ef25959f14c61aa76515fe301fa45a99 |
| Headers | show
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arm64: dts: ti: Disable clock output of the ethernet PHY
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diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts index 4bc0134c987d..3173f6eca7ca 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -222,6 +222,7 @@ &cpsw3g_mdio { cpsw3g_phy3: ethernet-phy@3 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <3>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; };
The clock on the ethernet1 PHY is turned on by default. This turns the clock off as we do not use it. Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com> --- arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts | 1 + 1 file changed, 1 insertion(+)