Message ID | 20240115130817.88456-5-prabhakar.mahadev-lad.rj@bp.renesas.com |
---|---|
State | New |
Headers | show |
Series | Add missing port pins for RZ/Five SoC | expand |
On Mon, Jan 15, 2024 at 2:08 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update > the gpio-ranges property in RZ/Five SoC DTSI. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> My Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> on v3 is still valid. > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > @@ -46,6 +46,10 @@ cpu0_intc: interrupt-controller { > }; > }; > > +&pinctrl { > + gpio-ranges = <&pinctrl 0 0 232>; > +}; > + > &soc { > dma-noncoherent; > interrupt-parent = <&plic>; I believe this has a hard dependency on the pinctrl driver changes, due to the following check in in rzg2l_gpio_register(): if (of_args.args[0] != 0 || of_args.args[1] != 0 || of_args.args[2] != pctrl->data->n_port_pins) { dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); return -EINVAL; } Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index d2272a0bfb61..aa3b1d2b999d 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -46,6 +46,10 @@ cpu0_intc: interrupt-controller { }; }; +&pinctrl { + gpio-ranges = <&pinctrl 0 0 232>; +}; + &soc { dma-noncoherent; interrupt-parent = <&plic>;