Message ID | 20240110102102.61587-2-tudor.ambarus@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | serial: samsung: gs101 updates and winter cleanup | expand |
On Wed, Jan 10, 2024 at 4:21 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > GS101's Connectivity Peripheral blocks (peric0/1 blocks) which > include the I3C and USI (I2C, SPI, UART) only allow 32-bit > register accesses. If using 8-bit register accesses, a SError > Interrupt is raised causing the system unusable. > > Instead of specifying the reg-io-width = 4 everywhere, for each node, > the requirement should be deduced from the compatible. > > Prepare the samsung tty driver to allow IO types different than > UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all > its 8 bits are exposed to uapi. We can't make NULL checks on it to > verify if it's set, thus always set it from the driver's data. > Use u8 for the ``iotype`` member of ``struct s3c24xx_uart_info`` to > emphasize that the iotype is an 8 bit mask. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > drivers/tty/serial/samsung_tty.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > index 71d17d804fda..b8fe9df20202 100644 > --- a/drivers/tty/serial/samsung_tty.c > +++ b/drivers/tty/serial/samsung_tty.c > @@ -84,6 +84,7 @@ struct s3c24xx_uart_info { > unsigned long clksel_mask; > unsigned long clksel_shift; > unsigned long ucon_mask; > + u8 iotype; > > /* uart port features */ > > @@ -1742,7 +1743,6 @@ static void s3c24xx_serial_init_port_default(int index) { > > spin_lock_init(&port->lock); > > - port->iotype = UPIO_MEM; > port->uartclk = 0; > port->fifosize = 16; > port->flags = UPF_BOOT_AUTOCONF; > @@ -1989,6 +1989,8 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) > break; > } > > + ourport->port.iotype = ourport->info->iotype; > + > if (np) { > of_property_read_u32(np, > "samsung,uart-fifosize", &ourport->port.fifosize); > @@ -2399,6 +2401,7 @@ static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { > .name = "Samsung S3C6400 UART", > .type = TYPE_S3C6400, > .port_type = PORT_S3C6400, > + .iotype = UPIO_MEM, > .fifosize = 64, > .has_divslot = 1, > .rx_fifomask = S3C2440_UFSTAT_RXMASK, > @@ -2428,6 +2431,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { > .name = "Samsung S5PV210 UART", > .type = TYPE_S3C6400, > .port_type = PORT_S3C6400, > + .iotype = UPIO_MEM, > .has_divslot = 1, > .rx_fifomask = S5PV210_UFSTAT_RXMASK, > .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, > @@ -2457,6 +2461,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { > .name = "Samsung Exynos UART", \ > .type = TYPE_S3C6400, \ > .port_type = PORT_S3C6400, \ > + .iotype = UPIO_MEM, \ > .has_divslot = 1, \ > .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ > .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ > @@ -2517,6 +2522,7 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { > .name = "Apple S5L UART", > .type = TYPE_APPLE_S5L, > .port_type = PORT_8250, > + .iotype = UPIO_MEM, > .fifosize = 16, > .rx_fifomask = S3C2410_UFSTAT_RXMASK, > .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, > @@ -2546,6 +2552,7 @@ static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { > .name = "Axis ARTPEC-8 UART", > .type = TYPE_S3C6400, > .port_type = PORT_S3C6400, > + .iotype = UPIO_MEM, > .fifosize = 64, > .has_divslot = 1, > .rx_fifomask = S5PV210_UFSTAT_RXMASK, > -- > 2.43.0.472.g3155946c3a-goog > >
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 71d17d804fda..b8fe9df20202 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -84,6 +84,7 @@ struct s3c24xx_uart_info { unsigned long clksel_mask; unsigned long clksel_shift; unsigned long ucon_mask; + u8 iotype; /* uart port features */ @@ -1742,7 +1743,6 @@ static void s3c24xx_serial_init_port_default(int index) { spin_lock_init(&port->lock); - port->iotype = UPIO_MEM; port->uartclk = 0; port->fifosize = 16; port->flags = UPF_BOOT_AUTOCONF; @@ -1989,6 +1989,8 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) break; } + ourport->port.iotype = ourport->info->iotype; + if (np) { of_property_read_u32(np, "samsung,uart-fifosize", &ourport->port.fifosize); @@ -2399,6 +2401,7 @@ static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { .name = "Samsung S3C6400 UART", .type = TYPE_S3C6400, .port_type = PORT_S3C6400, + .iotype = UPIO_MEM, .fifosize = 64, .has_divslot = 1, .rx_fifomask = S3C2440_UFSTAT_RXMASK, @@ -2428,6 +2431,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .name = "Samsung S5PV210 UART", .type = TYPE_S3C6400, .port_type = PORT_S3C6400, + .iotype = UPIO_MEM, .has_divslot = 1, .rx_fifomask = S5PV210_UFSTAT_RXMASK, .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, @@ -2457,6 +2461,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .name = "Samsung Exynos UART", \ .type = TYPE_S3C6400, \ .port_type = PORT_S3C6400, \ + .iotype = UPIO_MEM, \ .has_divslot = 1, \ .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ @@ -2517,6 +2522,7 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { .name = "Apple S5L UART", .type = TYPE_APPLE_S5L, .port_type = PORT_8250, + .iotype = UPIO_MEM, .fifosize = 16, .rx_fifomask = S3C2410_UFSTAT_RXMASK, .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, @@ -2546,6 +2552,7 @@ static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { .name = "Axis ARTPEC-8 UART", .type = TYPE_S3C6400, .port_type = PORT_S3C6400, + .iotype = UPIO_MEM, .fifosize = 64, .has_divslot = 1, .rx_fifomask = S5PV210_UFSTAT_RXMASK,