| Message ID | 20240109125814.3691033-12-tudor.ambarus@linaro.org |
|---|---|
| State | Accepted |
| Commit | 6d44d1a1fb62e033dde18d73cbbb604663eb84c0 |
| Headers | show |
| Series | [v3,01/12] dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit | expand |
On 1/16/24 18:03, Sam Protsenko wrote: >> USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 >> doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the >> selection of the protocol is intentionally left for the board dts file. >> >> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> >> --- >> v3: reorder usi8 clock order (thanks Andre'!). Did not make any >> difference at testing as the usi driver treats the clocks in bulk. >> v2: >> - identify and use gate clocks instead of dividers >> - move cells and pinctrl properties from dts to dtsi >> - move IRQ type constant on the previous line >> >> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++ >> 1 file changed, 29 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> index 6aa25cc4676e..f14a24628d04 100644 >> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 { >> interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; >> }; >> >> + usi8: usi@109700c0 { >> + compatible = "google,gs101-usi", >> + "samsung,exynos850-usi"; >> + reg = <0x109700c0 0x20>; >> + ranges; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, >> + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; >> + clock-names = "pclk", "ipclk"; >> + samsung,sysreg = <&sysreg_peric0 0x101c>; > I'd also add samsung,mode for the "default" USI mode here, just to > avoid providing it later in the board's dts. But that's a matter of > taste I guess. > USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dts file. I wanted to emphasize that USI8 doesn't have any HW defaults and its mode must be chosen by each particular board. I mentioned the same in the commit message, please tell if you feel it needs updating. Cheers, ta
On Wed, Jan 17, 2024 at 9:08 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > > > On 1/16/24 18:03, Sam Protsenko wrote: > >> USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 > >> doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the > >> selection of the protocol is intentionally left for the board dts file. > >> > >> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > >> --- > >> v3: reorder usi8 clock order (thanks Andre'!). Did not make any > >> difference at testing as the usi driver treats the clocks in bulk. > >> v2: > >> - identify and use gate clocks instead of dividers > >> - move cells and pinctrl properties from dts to dtsi > >> - move IRQ type constant on the previous line > >> > >> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++ > >> 1 file changed, 29 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > >> index 6aa25cc4676e..f14a24628d04 100644 > >> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > >> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > >> @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 { > >> interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; > >> }; > >> > >> + usi8: usi@109700c0 { > >> + compatible = "google,gs101-usi", > >> + "samsung,exynos850-usi"; > >> + reg = <0x109700c0 0x20>; > >> + ranges; > >> + #address-cells = <1>; > >> + #size-cells = <1>; > >> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, > >> + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; > >> + clock-names = "pclk", "ipclk"; > >> + samsung,sysreg = <&sysreg_peric0 0x101c>; > > I'd also add samsung,mode for the "default" USI mode here, just to > > avoid providing it later in the board's dts. But that's a matter of > > taste I guess. > > > > USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 > doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the > selection of the protocol is intentionally left for the board dts file. > > I wanted to emphasize that USI8 doesn't have any HW defaults and its > mode must be chosen by each particular board. > > I mentioned the same in the commit message, please tell if you feel it > needs updating. > No, thanks, everything LGTM, I already added my R-b tag above. > Cheers, > ta
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 6aa25cc4676e..f14a24628d04 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 { interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; }; + usi8: usi@109700c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; + + hsi2c_8: i2c@10970000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + usi_uart: usi@10a000c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi";
USI8 I2C is used to communicate with an eeprom found on the battery connector. Define USI8 in I2C configuration. USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dts file. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- v3: reorder usi8 clock order (thanks Andre'!). Did not make any difference at testing as the usi driver treats the clocks in bulk. v2: - identify and use gate clocks instead of dividers - move cells and pinctrl properties from dts to dtsi - move IRQ type constant on the previous line arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+)