| Message ID | 20240109-phy-qmp-merge-common-v1-8-572899a14318@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: qcom: merge common register defines in QMP drivers | expand |
On Tue, 9 Jan 2024 at 04:04, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > Follow the example of the rest of the QMP PHY drivers and move SGMII PCS > registers to a separate header file. > > Cc: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- I'm typically opposed to the idea of putting defines used by a single driver in a separate header (for what reason?) but if that's consistent with the rest of existing drivers then ok. Bartosz
On Tue, Jan 09, 2024 at 05:04:06AM +0200, Dmitry Baryshkov wrote: > Follow the example of the rest of the QMP PHY drivers and move SGMII PCS > registers to a separate header file. > > Cc: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Probably not necessary to test, but I took this for a spin without any noticeable regression to networking with stmmac (which afaik is the only user of this driver so far). Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h | 20 +++++++++ > drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 64 +++++++++++---------------- > 2 files changed, 47 insertions(+), 37 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h > new file mode 100644 > index 000000000000..4d8c962f5e0f > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2023, Linaro Limited > + */ > + > +#ifndef QCOM_PHY_QMP_PCS_SGMII_H_ > +#define QCOM_PHY_QMP_PCS_SGMII_H_ > + > +#define QPHY_PCS_PHY_START 0x000 > +#define QPHY_PCS_POWER_DOWN_CONTROL 0x004 > +#define QPHY_PCS_SW_RESET 0x008 > +#define QPHY_PCS_LINE_RESET_TIME 0x00c > +#define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020 > +#define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028 > +#define QPHY_PCS_PCS_READY_STATUS 0x094 > +#define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8 > +#define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc > +#define QPHY_PCS_SGMII_MISC_CTRL8 0x118 > + > +#endif > diff --git a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c > index 233f9b70c673..5b1c82459c12 100644 > --- a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c > +++ b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c > @@ -11,6 +11,7 @@ > #include <linux/platform_device.h> > #include <linux/regmap.h> > > +#include "phy-qcom-qmp-pcs-sgmii.h" > #include "phy-qcom-qmp-qserdes-com-v5.h" > #include "phy-qcom-qmp-qserdes-txrx-v5.h" > > @@ -19,17 +20,6 @@ > #define QSERDES_TX 0x400 > #define QSERDES_PCS 0xc00 > > -#define QSERDES_PCS_PHY_START (QSERDES_PCS + 0x0) > -#define QSERDES_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4) > -#define QSERDES_PCS_SW_RESET (QSERDES_PCS + 0x8) > -#define QSERDES_PCS_LINE_RESET_TIME (QSERDES_PCS + 0xc) > -#define QSERDES_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES_PCS + 0x20) > -#define QSERDES_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES_PCS + 0x28) > -#define QSERDES_PCS_TX_MID_TERM_CTRL1 (QSERDES_PCS + 0xd8) > -#define QSERDES_PCS_TX_MID_TERM_CTRL2 (QSERDES_PCS + 0xdc) > -#define QSERDES_PCS_SGMII_MISC_CTRL8 (QSERDES_PCS + 0x118) > -#define QSERDES_PCS_PCS_READY_STATUS (QSERDES_PCS + 0x94) > - > #define QSERDES_COM_C_READY BIT(0) > #define QSERDES_PCS_READY BIT(0) > #define QSERDES_PCS_SGMIIPHY_READY BIT(7) > @@ -43,8 +33,8 @@ struct qcom_dwmac_sgmii_phy_data { > > static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap) > { > - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); > - regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); > > regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); > regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); > @@ -118,21 +108,21 @@ static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap) > regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); > regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); > > - regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); > - regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); > - regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); > - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83); > - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); > - regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x0C); > - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x0C); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); > > - regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); > } > > static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap) > { > - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); > - regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); > > regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); > regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); > @@ -206,15 +196,15 @@ static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap) > regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); > regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); > > - regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); > - regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); > - regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); > - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83); > - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); > - regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x8C); > - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x8C); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); > > - regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01); > + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); > } > > static inline int > @@ -251,14 +241,14 @@ static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy) > } > > if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, > - QSERDES_PCS_PCS_READY_STATUS, > + QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, > QSERDES_PCS_READY)) { > dev_err(dev, "PCS_READY timed-out"); > return -ETIMEDOUT; > } > > if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, > - QSERDES_PCS_PCS_READY_STATUS, > + QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, > QSERDES_PCS_SGMIIPHY_READY)) { > dev_err(dev, "SGMIIPHY_READY timed-out"); > return -ETIMEDOUT; > @@ -285,11 +275,11 @@ static int qcom_dwmac_sgmii_phy_power_off(struct phy *phy) > { > struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy); > > - regmap_write(data->regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); > - regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x01); > + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); > + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); > udelay(100); > - regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x00); > - regmap_write(data->regmap, QSERDES_PCS_PHY_START, 0x01); > + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); > + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); > > clk_disable_unprepare(data->refclk); > > > -- > 2.39.2 > >
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h new file mode 100644 index 000000000000..4d8c962f5e0f --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_SGMII_H_ +#define QCOM_PHY_QMP_PCS_SGMII_H_ + +#define QPHY_PCS_PHY_START 0x000 +#define QPHY_PCS_POWER_DOWN_CONTROL 0x004 +#define QPHY_PCS_SW_RESET 0x008 +#define QPHY_PCS_LINE_RESET_TIME 0x00c +#define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020 +#define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028 +#define QPHY_PCS_PCS_READY_STATUS 0x094 +#define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8 +#define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc +#define QPHY_PCS_SGMII_MISC_CTRL8 0x118 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c index 233f9b70c673..5b1c82459c12 100644 --- a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c +++ b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c @@ -11,6 +11,7 @@ #include <linux/platform_device.h> #include <linux/regmap.h> +#include "phy-qcom-qmp-pcs-sgmii.h" #include "phy-qcom-qmp-qserdes-com-v5.h" #include "phy-qcom-qmp-qserdes-txrx-v5.h" @@ -19,17 +20,6 @@ #define QSERDES_TX 0x400 #define QSERDES_PCS 0xc00 -#define QSERDES_PCS_PHY_START (QSERDES_PCS + 0x0) -#define QSERDES_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4) -#define QSERDES_PCS_SW_RESET (QSERDES_PCS + 0x8) -#define QSERDES_PCS_LINE_RESET_TIME (QSERDES_PCS + 0xc) -#define QSERDES_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES_PCS + 0x20) -#define QSERDES_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES_PCS + 0x28) -#define QSERDES_PCS_TX_MID_TERM_CTRL1 (QSERDES_PCS + 0xd8) -#define QSERDES_PCS_TX_MID_TERM_CTRL2 (QSERDES_PCS + 0xdc) -#define QSERDES_PCS_SGMII_MISC_CTRL8 (QSERDES_PCS + 0x118) -#define QSERDES_PCS_PCS_READY_STATUS (QSERDES_PCS + 0x94) - #define QSERDES_COM_C_READY BIT(0) #define QSERDES_PCS_READY BIT(0) #define QSERDES_PCS_SGMIIPHY_READY BIT(7) @@ -43,8 +33,8 @@ struct qcom_dwmac_sgmii_phy_data { static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap) { - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); - regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); @@ -118,21 +108,21 @@ static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap) regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); - regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); - regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); - regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83); - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); - regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x0C); - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x0C); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); - regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); } static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap) { - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); - regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); @@ -206,15 +196,15 @@ static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap) regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); - regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); - regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); - regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83); - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); - regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x8C); - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x8C); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); - regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); } static inline int @@ -251,14 +241,14 @@ static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy) } if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, - QSERDES_PCS_PCS_READY_STATUS, + QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, QSERDES_PCS_READY)) { dev_err(dev, "PCS_READY timed-out"); return -ETIMEDOUT; } if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, - QSERDES_PCS_PCS_READY_STATUS, + QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, QSERDES_PCS_SGMIIPHY_READY)) { dev_err(dev, "SGMIIPHY_READY timed-out"); return -ETIMEDOUT; @@ -285,11 +275,11 @@ static int qcom_dwmac_sgmii_phy_power_off(struct phy *phy) { struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy); - regmap_write(data->regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); - regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x01); + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); udelay(100); - regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x00); - regmap_write(data->regmap, QSERDES_PCS_PHY_START, 0x01); + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); clk_disable_unprepare(data->refclk);
Follow the example of the rest of the QMP PHY drivers and move SGMII PCS registers to a separate header file. Cc: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h | 20 +++++++++ drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 64 +++++++++++---------------- 2 files changed, 47 insertions(+), 37 deletions(-)