diff mbox series

arm64: dts: rockchip: enable NanoPC-T6 MiniPCIe power

Message ID 20240107223714.8158-1-sigmaris@gmail.com
State Superseded
Headers show
Series arm64: dts: rockchip: enable NanoPC-T6 MiniPCIe power | expand

Commit Message

Hugh Cole-Baker Jan. 7, 2024, 10:37 p.m. UTC
The NanoPC-T6 has a Mini PCIe slot intended to be used for a 4G or LTE
modem. This slot has no PCIe functionality, only its USB 2.0 pins are
wired to the SoC, and its USIM pins are wired to a SIM card slot on the
board. Define the 3.3v supply for the slot so it can be used.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
---
I've based the names directly on the schematic [1] (page 29) which uses
VDD_4G_3.3V and 4G_LTE_PWREN for the supply and enable signal respectively.
This means the enable pinctrl label needs an initial underscore. I'm OK with
changing that if it's considered ugly or there's a better suggested name.

[1]: https://wiki.friendlyelec.com/wiki/images/9/97/NanoPC-T6_2301_SCH.PDF

 .../boot/dts/rockchip/rk3588-nanopc-t6.dts      | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
index d7722772ecd8..d91af387f7c4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
@@ -159,6 +159,18 @@  vcc3v3_pcie30: vcc3v3-pcie30-regulator {
 		regulator-max-microvolt = <3300000>;
 		vin-supply = <&vcc5v0_sys>;
 	};
+
+	vdd_4g_3v3: vdd-4g-3v3-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&_4g_lte_pwren>;
+		regulator-name = "vdd_4g_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
 };
 
 &combphy0_ps {
@@ -504,6 +516,10 @@  pcie_m2_1_pwren: pcie-m21-pwren {
 	};
 
 	usb {
+		_4g_lte_pwren: 4g-lte-pwren {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
 		typec5v_pwren: typec5v-pwren {
 			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
@@ -884,6 +900,7 @@  &uart2 {
 };
 
 &u2phy2_host {
+	phy-supply = <&vdd_4g_3v3>;
 	status = "okay";
 };