| Message ID | 20231227170919.8771-3-othacehe@gnu.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Variscite VAR-SOM-MX93 support | expand |
Hi Mathieu, Am 27.12.23 um 18:09 schrieb Mathieu Othacehe: > Add DTSI for Variscite VAR-SOM-MX93 System on Module and DTS for Variscite > VAR-SOM-MX93 on Symphony evaluation board. > > This version comes with: > - NXP i.MX 93 Dual, 1.7GHz, Cortex-A55 + Cortex-M33 > - 2 GB of RAM > - 16GB eMMC > - 802.11ax/ac/a/b/g/n WiFi with 5.3 Bluetooth > - CAN bus > - Audio codec > > Reviewed-by: Fabio Estevam <festevam@gmail.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Mathieu Othacehe <othacehe@gnu.org> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../dts/freescale/imx93-var-som-symphony.dts | 303 ++++++++++++++++++ > .../boot/dts/freescale/imx93-var-som.dtsi | 111 +++++++ > 3 files changed, 415 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts > create mode 100644 arch/arm64/boot/dts/freescale/imx93-var-som.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 2e027675d7bb..a6f1700961e3 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -203,6 +203,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb > > imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo > imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo > diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts > new file mode 100644 > index 000000000000..3b7a01fb1b51 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts > @@ -0,0 +1,303 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2021 NXP > + * Copyright 2023 Variscite Ltd. > + */ > + > +/dts-v1/; > + > +#include "imx93-var-som.dtsi" > + > +/{ > + model = "Variscite VAR-SOM-MX93 on Symphony evaluation board"; > + compatible = "variscite,var-som-mx93-symphony", > + "variscite,var-som-mx93", "fsl,imx93"; > + > + aliases { > + ethernet0 = &eqos; > + ethernet1 = &fec; > + }; > + > + chosen { > + stdout-path = &lpuart1; > + }; > + > + /* > + * Needed only for Symphony <= v1.5 > + */ > + reg_fec_phy: regulator-fec-phy { > + compatible = "regulator-fixed"; > + regulator-name = "fec-phy"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-enable-ramp-delay = <20000>; > + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > + regulator-name = "VSD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; > + off-on-delay-us = <20000>; > + enable-active-high; > + }; > + > + reg_vref_1v8: regulator-adc-vref { > + compatible = "regulator-fixed"; > + regulator-name = "vref_1v8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + ethosu_mem: ethosu-region@88000000 { > + compatible = "shared-dma-pool"; > + reusable; > + reg = <0x0 0x88000000 0x0 0x8000000>; > + }; > + > + vdev0vring0: vdev0vring0@87ee0000 { > + reg = <0 0x87ee0000 0 0x8000>; > + no-map; > + }; > + > + vdev0vring1: vdev0vring1@87ee8000 { > + reg = <0 0x87ee8000 0 0x8000>; > + no-map; > + }; > + > + vdev1vring0: vdev1vring0@87ef0000 { > + reg = <0 0x87ef0000 0 0x8000>; > + no-map; > + }; > + > + vdev1vring1: vdev1vring1@87ef8000 { > + reg = <0 0x87ef8000 0 0x8000>; > + no-map; > + }; > + > + rsc_table: rsc-table@2021f000 { > + reg = <0 0x2021f000 0 0x1000>; > + no-map; > + }; > + > + vdevbuffer: vdevbuffer@87f00000 { > + compatible = "shared-dma-pool"; > + reg = <0 0x87f00000 0 0x100000>; > + no-map; > + }; > + > + ele_reserved: ele-reserved@87de0000 { > + compatible = "shared-dma-pool"; > + reg = <0 0x87de0000 0 0x100000>; > + no-map; > + }; > + }; > +}; > + > +/* Use external instead of internal RTC*/ > +&bbnsm_rtc { > + status = "disabled"; > +}; > + > +&eqos { > + mdio { > + ethphy1: ethernet-phy@5 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <5>; > + qca,disable-smarteee; > + eee-broken-1000t; > + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; > + reset-assert-us = <10000>; > + reset-deassert-us = <20000>; > + vddio-supply = <&vddio1>; > + > + vddio1: vddio-regulator { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + }; > + }; > +}; > + > +&fec { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec>; > + phy-mode = "rgmii"; > + phy-handle = <ðphy1>; > + phy-supply = <®_fec_phy>; > + status = "okay"; > +}; > + > +&flexcan1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_fec: fecgrp { > + fsl,pins = < > + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e > + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e > + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e > + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e > + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe > + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e > + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e > + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e > + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e > + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e > + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe > + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e > + >; > + }; > + > + pinctrl_flexcan1: flexcan1grp { > + fsl,pins = < > + MX93_PAD_PDM_CLK__CAN1_TX 0x139e > + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e > + >; > + }; > + > + pinctrl_lpi2c1: lpi2c1grp { > + fsl,pins = < > + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e > + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e > + >; > + }; > + > + pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { > + fsl,pins = < > + MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e > + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e > + >; > + }; > + > + pinctrl_lpi2c5: lpi2c5grp { > + fsl,pins = < > + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e > + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e > + >; > + }; > + > + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { > + fsl,pins = < > + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e > + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e > + >; > + }; > + > + pinctrl_pca9534: pca9534grp { > + fsl,pins = < > + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e > + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e > + >; > + }; > + > + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { > + fsl,pins = < > + MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe > + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe > + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe > + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe > + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe > + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe > + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > + fsl,pins = < > + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e > + >; > + }; > +}; > + > +&lpi2c1 { > + clock-frequency = <400000>; > + pinctrl-names = "default", "sleep", "gpio"; > + pinctrl-0 = <&pinctrl_lpi2c1>; > + pinctrl-1 = <&pinctrl_lpi2c1_gpio>; > + pinctrl-2 = <&pinctrl_lpi2c1_gpio>; > + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; > + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; > + status = "okay"; > + > + /* DS1337 RTC module */ > + rtc@68 { > + compatible = "dallas,ds1337"; > + reg = <0x68>; > + }; > +}; > + > +&lpi2c5 { > + clock-frequency = <400000>; > + pinctrl-names = "default", "sleep", "gpio"; > + pinctrl-0 = <&pinctrl_lpi2c5>; > + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; > + pinctrl-2 = <&pinctrl_lpi2c5_gpio>; > + scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; > + sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; > + status = "okay"; > + > + pca9534: gpio@20 { > + compatible = "nxp,pca9534"; > + reg = <0x20>; > + gpio-controller; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pca9534>; > + interrupt-parent = <&gpio3>; > + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; > + #gpio-cells = <2>; > + wakeup-source; > + }; there are neither gpio-line-names defined for this GPIO expander nor the SOC. Are there no GPIOs which can be accessed from userspace? Best regards
Hello Stefan, > there are neither gpio-line-names defined for this GPIO expander nor the > SOC. Are there no GPIOs which can be accessed from userspace? The carrier board schematic is here: https://www.variscite.com/wp-content/uploads/2023/01/symphony-board_VAR-SOM-MX93.pdf All the pin headers are mapped to specific functions. On the other, already mainlined device-trees, that are based on the same "Symphony" carrier board, there are however gpio-keys for three buttons: gpio-keys { compatible = "gpio-keys"; key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; }; key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; }; }; I can add that in v5. Thanks, Mathieu
Hi Mathieu, Am 29.12.23 um 14:00 schrieb Mathieu Othacehe: > Hello Stefan, > >> there are neither gpio-line-names defined for this GPIO expander nor the >> SOC. Are there no GPIOs which can be accessed from userspace? > The carrier board schematic is here: > https://www.variscite.com/wp-content/uploads/2023/01/symphony-board_VAR-SOM-MX93.pdf Thanks this helps. > > All the pin headers are mapped to specific functions. On the other, > already mainlined device-trees, that are based on the same "Symphony" > carrier board, there are however gpio-keys for three buttons: > > > gpio-keys { > compatible = "gpio-keys"; > > key-back { > label = "Back"; > gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; > linux,code = <KEY_BACK>; > }; > > key-home { > label = "Home"; > gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; > linux,code = <KEY_HOME>; > }; > > key-menu { > label = "Menu"; > gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; > linux,code = <KEY_MENU>; > }; > }; > > I can add that in v5. yes please. I also saw in the other Symphony DTS a LED for heartbeat. Is it usable, too? According to the datasheet the SOM expose 7 UARTs, but only the debug UART is enable. What is the reason for this? Btw the commit log mentions a Wifi (via SDIO?) and audio interface. This is currently not supported by Linux? Thanks > > Thanks, > > Mathieu
Hey, > I also saw in the other Symphony DTS a LED for heartbeat. Is it usable, too? Yes, I will add it to in v5. > According to the datasheet the SOM expose 7 UARTs, but only the debug > UART is enable. What is the reason for this? So those 7 UARTs are: UART1: console UART2: used by the microphone UART3: used by the resistive touch UART4: used by the ethernet/resistive touch UART5: on J18.4,6,8,10 (used by BT) UART6: on J18.7 and J18.9 (available) UART7: on J18.3 and J18.5 (used by the M33 firmware) I will enable UART6, and add a mention about UART7, something like: /* J18.7, J18.9 */ &lpuart6 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart6>; status = "okay"; }; /* J18.3, J18.5 - used by M33 firmware */ &lpuart7 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart7>; status = "disabled"; }; > Btw the commit log mentions a Wifi (via SDIO?) and audio interface. This > is currently not supported by Linux? I am not sure about that, and I would prefer to study that a bit later on if that's OK :) I can remove it from the commit log as this is misleading as not already supported / tested. Thanks, Mathieu
Hi, Am 29.12.23 um 17:48 schrieb Mathieu Othacehe: > Hey, > >> I also saw in the other Symphony DTS a LED for heartbeat. Is it usable, too? > Yes, I will add it to in v5. > >> According to the datasheet the SOM expose 7 UARTs, but only the debug >> UART is enable. What is the reason for this? > So those 7 UARTs are: > > UART1: console > UART2: used by the microphone > UART3: used by the resistive touch > UART4: used by the ethernet/resistive touch > UART5: on J18.4,6,8,10 (used by BT) > UART6: on J18.7 and J18.9 (available) > UART7: on J18.3 and J18.5 (used by the M33 firmware) > > I will enable UART6, and add a mention about UART7, something like: > > /* J18.7, J18.9 */ > &lpuart6 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_uart6>; > status = "okay"; > }; > > /* J18.3, J18.5 - used by M33 firmware */ > &lpuart7 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_uart7>; > status = "disabled"; > }; in case this is used by the M33 firmware, this applies to all i.MX93 so we don't need this. Just enable UART6 and keep UART7. >> Btw the commit log mentions a Wifi (via SDIO?) and audio interface. This >> is currently not supported by Linux? > I am not sure about that, and I would prefer to study that a bit later > on if that's OK :) I can remove it from the commit log as this is > misleading as not already supported / tested. This sounds good. No need to have it all at first. > > Thanks, > > Mathieu > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 2e027675d7bb..a6f1700961e3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -203,6 +203,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts new file mode 100644 index 000000000000..3b7a01fb1b51 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + * Copyright 2023 Variscite Ltd. + */ + +/dts-v1/; + +#include "imx93-var-som.dtsi" + +/{ + model = "Variscite VAR-SOM-MX93 on Symphony evaluation board"; + compatible = "variscite,var-som-mx93-symphony", + "variscite,var-som-mx93", "fsl,imx93"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; + + chosen { + stdout-path = &lpuart1; + }; + + /* + * Needed only for Symphony <= v1.5 + */ + reg_fec_phy: regulator-fec-phy { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ethosu_mem: ethosu-region@88000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 0x88000000 0x0 0x8000000>; + }; + + vdev0vring0: vdev0vring0@87ee0000 { + reg = <0 0x87ee0000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@87ee8000 { + reg = <0 0x87ee8000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@87ef0000 { + reg = <0 0x87ef0000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@87ef8000 { + reg = <0 0x87ef8000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@87f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x87f00000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@87de0000 { + compatible = "shared-dma-pool"; + reg = <0 0x87de0000 0 0x100000>; + no-map; + }; + }; +}; + +/* Use external instead of internal RTC*/ +&bbnsm_rtc { + status = "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + qca,disable-smarteee; + eee-broken-1000t; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { + fsl,pins = < + MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1_gpio>; + pinctrl-2 = <&pinctrl_lpi2c1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + /* DS1337 RTC module */ + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&lpi2c5 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + pinctrl-2 = <&pinctrl_lpi2c5_gpio>; + scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + wakeup-source; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +/* Watchdog */ +&wdog3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi new file mode 100644 index 000000000000..6c77b886666b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2023 Variscite Ltd. + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/{ + model = "Variscite VAR-SOM-MX93 module"; + compatible = "variscite,var-som-mx93", "fsl,imx93"; + + mmc_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; + + reg_eqos_phy: regulator-eqos-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eqos_phy>; + regulator-name = "eth_phy_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + regulator-always-on; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + phy-supply = <®_eqos_phy>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <1000000>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_reg_eqos_phy: regeqosgrp { + fsl,pins = < + MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +};