diff mbox series

arm64: dts: qcom: sc8280xp: Describe the SMMUv3

Message ID 20231219-topic-8280_smmuv3-v1-1-efeb32b2655b@linaro.org
State New
Headers show
Series arm64: dts: qcom: sc8280xp: Describe the SMMUv3 | expand

Commit Message

Konrad Dybcio Dec. 19, 2023, 8:06 p.m. UTC 
SC8280XP actually has a third SMMU, which can be seen in e.g. the IORT
ACPI table.

Unfortunately though, the secure firmware seems to be configured in a
way such that Linux can't touch it, not even read back the ID registers.

Add it for hardware description completeness. Do note the reg space
size is only an educated guess.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)


---
base-commit: aa4db8324c4d0e67aa4670356df4e9fae14b4d37
change-id: 20231219-topic-8280_smmuv3-51d8795af7ec

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index febf28356ff8..391aa783251d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4078,6 +4078,22 @@  tlmm: pinctrl@f100000 {
 			wakeup-parent = <&pdc>;
 		};
 
+		iommu@14f80000 {
+			compatible = "arm,smmu-v3";
+			reg = <0 0x14f80000 0 0x80000>;
+			interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eventq",
+					  "gerror",
+					  "cmdq-sync";
+			#iommu-cells = <1>;
+			dma-coherent;
+
+			/* The secure firmware prevents register access from Linux */
+			status = "reserved";
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
 			reg = <0 0x15000000 0 0x100000>;