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[v3] arm64: dts: ti: k3-am654-icssg2: Enable PHY interrupt for ICSSG2 PHY0

Message ID 20231215054721.1975642-1-s-vadapalli@ti.com
State New
Headers show
Series [v3] arm64: dts: ti: k3-am654-icssg2: Enable PHY interrupt for ICSSG2 PHY0 | expand

Commit Message

Siddharth Vadapalli Dec. 15, 2023, 5:47 a.m. UTC 
Enable interrupt mode of operation of the DP83867 Ethernet PHY which is
used by ICSSG2. The DP83867 PHY driver already supports interrupt handling
for interrupts generated by the PHY. Thus, add the necessary device-tree
support to enable it.

Since the GPIO1_87 line is muxed with EXT_REFCLK1 and SYNC1_OUT, update
the pinmux to select GPIO1_87 for routing the interrupt.

The GPIO1_87 interrupt line is shared by both the PHYs used by ICSSG2 due
to the board design. Since the SoC only supports Edge-Triggered interrupts
and Edge-Triggered interrupts cannot be shared, enable interrupt mode of
operation for ICSSG2 PHY0 alone while ICSSG2 PHY1 shall continue operating
in polled mode.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: MD Danish Anwar <danishanwar@ti.com>
---
Hello,

This patch is based on linux-next tagged next-20231215.

v2:
https://lore.kernel.org/r/20231213080216.1710730-1-s-vadapalli@ti.com/
Changes since v2:
- Rebased patch on next-20231215.
- As pointed out by Nishanth Menon <nm@ti.com> at:
  https://lore.kernel.org/r/20231213123819.tqh3lm2ceir3qjbk@swimmer/
  the interrupt being shared between both the PHYs is an Edge-Triggered
  interrupt, due to which it shouldn't be shared. Thus, as discussed at:
  https://lore.kernel.org/r/0cef8f50-6608-cf3d-ad62-1afd3f5560ea@ti.com/
  the interrupt shall be dedicated to ICSSG2 PHY0 while ICSSG2 PHY1 shall
  continue operating in polled mode.
- Removed interrupt specific configuration from icssg2_phy1 which was
  present in the v2 patch.
- Added comment above icssg2_phy0 indicating why the interrupt mode of
  operation is only being enabled for icssg2_phy0 and not for icssg2_phy1.
- Updated commit message to match the new implementation.

v1:
https://lore.kernel.org/r/20231120063159.539306-1-s-vadapalli@ti.com/
Changes since v1:
- Rebased patch on next-20231213.
- Collected Reviewed-by tag from
  MD Danish Anwar <danishanwar@ti.com>
- Moved pinctrl from MDIO node to Ethernet PHY node based on feedback from
  Nishanth Menon <nm@ti.com>
- Replaced the hard-coded value 0x2 with IRQ_TYPE_EDGE_FALLING for
  setting the interrupt trigger type and level flag based on feedback from
  Nishanth Menon <nm@ti.com>
- Included dt-bindings/interrupt-controller/irq.h in the overlay.
- Updated commit message with details of the pinmux resource allocation.

Regards,
Siddharth.

 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 23 +++++++++++++++++++++
 1 file changed, 23 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
index ec8cf20ca3ac..cce3f60904f1 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
+++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
@@ -8,6 +8,7 @@ 
 /dts-v1/;
 /plugin/;
 
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/net/ti-dp83867.h>
 #include "k3-pinctrl.h"
 
@@ -124,6 +125,15 @@  AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
 	};
 };
 
+&main_pmx1 {
+	/* Select GPIO1_87 for ICSSG2 PHY interrupt */
+	icssg2_phy_irq_pins_default: icssg2-phy-irq-default-pins {
+		pinctrl-single,pins = <
+			AM65X_IOPAD(0x0014, PIN_INPUT, 7) /* (A22) EXT_REFCLK1.GPIO1_87 */
+		>;
+	};
+};
+
 &icssg2_mdio {
 	status = "okay";
 	pinctrl-names = "default";
@@ -131,8 +141,21 @@  &icssg2_mdio {
 	#address-cells = <1>;
 	#size-cells = <0>;
 
+	/*
+	 * icssg2_phy0 and icssg2_phy1 share the same interrupt:
+	 * "GPIO1_87" due to the board design.
+	 * Since the SoC only supports Edge-Triggered interrupts and
+	 * Edge-Triggered interrupts cannot be shared, the interrupt will
+	 * be dedicated solely for icssg2_phy0's use while icssg2_phy1
+	 * shall continue operating in polled mode.
+	 */
 	icssg2_phy0: ethernet-phy@0 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&icssg2_phy_irq_pins_default>;
+
 		reg = <0>;
+		interrupt-parent = <&main_gpio1>;
+		interrupts = <87 IRQ_TYPE_EDGE_FALLING>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 	};