@@ -20771,6 +20771,13 @@ F: Documentation/devicetree/bindings/clock/starfive,jh81*.yaml
F: drivers/clk/starfive/jh8100
F: include/dt-bindings/clock/starfive?jh81*.h
+STARFIVE JH8100 RESET CONTROLLER DRIVERS
+M: Sia Jee Heng <jeeheng.sia@starfivetech.com>
+M: Ley Foon Tan <leyfoon.tan@starfivetech.com>
+S: Maintained
+F: drivers/reset/starfive/reset-starfive-jh81*
+F: include/dt-bindings/reset/starfive?jh81*.h
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
@@ -19,3 +19,11 @@ config RESET_STARFIVE_JH7110
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7110 SoC.
+
+config RESET_STARFIVE_JH8100
+ bool "StarFive JH8100 Reset Driver"
+ depends on AUXILIARY_BUS && CLK_STARFIVE_JH8100_SYS
+ select RESET_STARFIVE_COMMON
+ default ARCH_STARFIVE
+ help
+ This enables the reset controller driver for the StarFive JH8100 SoC.
@@ -3,3 +3,5 @@ obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
+
+obj-$(CONFIG_RESET_STARFIVE_JH8100) += reset-starfive-jh8100.o
new file mode 100644
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Reset driver for the StarFive JH8100 SoC
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jh8100-crg.h>
+#include <linux/auxiliary_bus.h>
+#include <soc/starfive/reset-starfive-common.h>
+
+#include "reset-starfive-common.h"
+
+struct jh8100_reset_info {
+ unsigned int nr_resets;
+ unsigned int assert_offset;
+ unsigned int status_offset;
+};
+
+static const struct jh8100_reset_info jh8100_sys_info = {
+ .nr_resets = SYSCRG_RESET_NR_RESETS,
+ .assert_offset = 0x1B4,
+ .status_offset = 0x1B8,
+};
+
+static const struct jh8100_reset_info jh8100_sys_nw_info = {
+ .nr_resets = SYSCRG_NW_RESET_NR_RESETS,
+ .assert_offset = 0xA4,
+ .status_offset = 0xA8,
+};
+
+static const struct jh8100_reset_info jh8100_sys_ne_info = {
+ .nr_resets = SYSCRG_NE_RESET_NR_RESETS,
+ .assert_offset = 0x2BC,
+ .status_offset = 0x2C4,
+};
+
+static const struct jh8100_reset_info jh8100_sys_sw_info = {
+ .nr_resets = SYSCRG_SW_RESET_NR_RESETS,
+ .assert_offset = 0x28,
+ .status_offset = 0x2C,
+};
+
+static const struct jh8100_reset_info jh8100_aon_info = {
+ .nr_resets = AONCRG_RESET_NR_RESETS,
+ .assert_offset = 0x104,
+ .status_offset = 0x108,
+};
+
+static int jh8100_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct jh8100_reset_info *info = (struct jh8100_reset_info *)
+ (id->driver_data);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
+ void __iomem *base = rdev->base;
+
+ if (!info || !base)
+ return -ENODEV;
+
+ return reset_starfive_register(&adev->dev,
+ adev->dev.parent->of_node,
+ base + info->assert_offset,
+ base + info->status_offset, NULL,
+ info->nr_resets, NULL);
+}
+
+static const struct auxiliary_device_id jh8100_reset_ids[] = {
+ {
+ .name = "clk_sys.rst-sys",
+ .driver_data = (kernel_ulong_t)&jh8100_sys_info,
+ },
+ {
+ .name = "clk_sys.rst-sys-nw",
+ .driver_data = (kernel_ulong_t)&jh8100_sys_nw_info,
+ },
+ {
+ .name = "clk_sys.rst-sys-ne",
+ .driver_data = (kernel_ulong_t)&jh8100_sys_ne_info,
+ },
+ {
+ .name = "clk_sys.rst-sys-sw",
+ .driver_data = (kernel_ulong_t)&jh8100_sys_sw_info,
+ },
+ {
+ .name = "clk_sys.rst-aon",
+ .driver_data = (kernel_ulong_t)&jh8100_aon_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, jh8100_reset_ids);
+
+static struct auxiliary_driver jh8100_reset_driver = {
+ .probe = jh8100_reset_probe,
+ .id_table = jh8100_reset_ids,
+};
+module_auxiliary_driver(jh8100_reset_driver);
+
+MODULE_AUTHOR("Joshua Yeong <joshua.yeong@starfivetech.com>");
+MODULE_AUTHOR("Sia Jee Heng <jeeheng.sia@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JH8100 reset driver");
+MODULE_LICENSE("GPL");