@@ -87,17 +87,17 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
do { \
- int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
- if (ret) { \
- return ret; \
+ int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
+ if (_ret) { \
+ return _ret; \
} \
} while (0)
#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
do { \
- int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
- if (ret) { \
- return ret; \
+ int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
+ if (_ret) { \
+ return _ret; \
} \
} while (0)
@@ -533,7 +533,6 @@ static int kvm_riscv_put_regs_core(CPUState *cs)
static int kvm_riscv_get_regs_csr(CPUState *cs)
{
- int ret = 0;
CPURISCVState *env = &RISCV_CPU(cs)->env;
KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
@@ -545,12 +544,12 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
- return ret;
+
+ return 0;
}
static int kvm_riscv_put_regs_csr(CPUState *cs)
{
- int ret = 0;
CPURISCVState *env = &RISCV_CPU(cs)->env;
KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
@@ -563,7 +562,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs)
KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
- return ret;
+ return 0;
}
static int kvm_riscv_get_regs_fp(CPUState *cs)