| Message ID | 20231127190857.1977974-4-enachman@marvell.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: cn913x: add COM Express boards | expand |
> > Now i'm confused. What does rd mean? > > > > I would expect RD mean Reference Design, and that is the complete device in > > its box. > > AC5X RD can either work as you would expect, as a complete standalone box using the internal CPU, or you can move the switch on the back of the box to "external" mode, and connect via an external cable a kit which would allow it to use an external CPU COM Express module, mounted on top of an interposer kit. > > > > > Yet, here you have RD for the carrier? > > > > The box itself is called cn9131-ac5x-carrier? > > > > This makes no sense to me. > > > > Maybe i'm understanding this all wrong, and its the carrier which you are > > producing a reference design for? The CPU module does not really matter? I > > So in this case, once the switch is set to external as explained above, the AC5X RD becomes part of the carrier solution. > This is a development/reference solution, not a full commercial solution, hence it has the flexibility to be configured in different modes of operation. O.K, now this make more sense. Please expand the documentation, in particularly the carrier, explaining how it can be used, and the .dts file about it giving a complete system, but again the carrier is the focus. Is the internal CPU open? Or is it a black box which only Marvell Firmware can use? I'm just wondering if we will need another .dtsi file describing the internal CPU, and a .dts file which includes both the carrier and the internal CPU .dtsi to give an image you can boot on the carrier? Andrew
> -----Original Message----- > From: Andrew Lunn <andrew@lunn.ch> > Sent: Wednesday, November 29, 2023 3:12 PM > To: Elad Nachman <enachman@marvell.com> > Cc: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > conor+dt@kernel.org; gregory.clement@bootlin.com; > sebastian.hesselbarth@gmail.com; pali@kernel.org; mrkiko.rs@gmail.com; > chris.packham@alliedtelesis.co.nz; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Yuval Caduri > <cyuval@marvell.com> > Subject: Re: [EXT] Re: [PATCH v6 3/3] arm64: dts: cn913x: add device trees for > COM Express boards > > > > Now i'm confused. What does rd mean? > > > > > > I would expect RD mean Reference Design, and that is the complete > > > device in its box. > > > > AC5X RD can either work as you would expect, as a complete standalone > > box using the internal CPU, or you can move the switch on the back of the > > box to "external" mode, and connect via an external cable a kit which would > > allow it to use an external CPU COM Express module, mounted on top of an > > interposer kit. > > > > > > > > Yet, here you have RD for the carrier? > > > > > > The box itself is called cn9131-ac5x-carrier? > > > > > > This makes no sense to me. > > > > > > Maybe i'm understanding this all wrong, and its the carrier which > > > you are producing a reference design for? The CPU module does not > > > really matter? I > > > > So in this case, once the switch is set to external as explained above, the > AC5X RD becomes part of the carrier solution. > > This is a development/reference solution, not a full commercial solution, >> hence it has the flexibility to be configured in different modes of operation. > > O.K, now this make more sense. Please expand the documentation, in > particularly the carrier, explaining how it can be used, and the .dts file about > it giving a complete system, but again the carrier is the focus. Will add comments on the dts and dtsi files on the next patch version. > > Is the internal CPU open? Or is it a black box which only Marvell Firmware > can use? I'm just wondering if we will need another .dtsi file describing the > internal CPU, and a .dts file which includes both the carrier and the internal > CPU .dtsi to give an image you can boot on the carrier? When the board boots in the internal (standalone) CPU mode, the following dts, which is Already upstreamed, is to be used to boot Linux on the internal, standalone CPU: arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts When the board boots in the external CPU mode, the internal CPU is disabled, and only the switch portion of the SOC acts as a PCIe end-point, Hence there is little use to describe a CPU which is disabled. In this mode, the AC5X RD carrier portion only provides a non-CPU PCIe end-point to the COM Express CPU module (in this case, containing the CN9131 CPU). There is no CPU booting in this mode on the carrier, only on the COM Express CPU module. What runs the Linux is the CN9131 on the COM Express CPU module, And it accesses the switch end-point on the AC5X RD portion of the carrier via PCIe. This is briefly documented (will elaborate further in next patch version) in the following file covered in the patch: arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi > > Andrew FYI, Elad.
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 79ac09b58a89..99b8cb3c49e1 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts new file mode 100644 index 000000000000..e83b9ae379ec --- /dev/null +++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the AC5X RD Type 7 Com Express carrier board, + * Utilizing the CN913x COM Express CPU module board. + * This specific board only maintains a PCIe link with the CPU CPU module + * module, which does not require any special DTS definitions. + */ + +#include "cn9131-db-comexpress.dtsi" +#include "ac5x-rd-carrier.dtsi" + +/ { + model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module"; + compatible = "marvell,cn9131-ac5x-carrier", "marvell,rd-ac5x-carrier", + "marvell,cn9131-cpu-module", "marvell,cn9131", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x2 0x00000000>; + }; + +}; diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi new file mode 100644 index 000000000000..fd45d5582233 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the AC5X RD Type 7 Com Express carrier board, + * This specific board only maintains a PCIe link with the CPU CPU module + * module, which does not require any special DTS definitions. + */ + +/ { + model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board"; + compatible = "marvell,rd-ac5x-carrier"; + +}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi new file mode 100644 index 000000000000..028496ebc473 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the CN9130-DB Com Express CPU module board. + */ + +#include "cn9130-db.dtsi" + +/ { + model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board"; + compatible = "marvell,cn9130-cpu-module", "marvell,cn9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + +}; + +&ap0_reg_sd_vccq { + regulator-max-microvolt = <1800000>; + states = <1800000 0x1 1800000 0x0>; + /delete-property/ gpios; +}; + +&cp0_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_usb3_vbus1 { + /delete-property/ gpio; +}; + +&cp0_reg_sd_vcc { + status = "disabled"; +}; + +&cp0_reg_sd_vccq { + status = "disabled"; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_eth0 { + status = "disabled"; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_eth2 { + status = "disabled"; +}; + +&cp0_mdio { + status = "okay"; + pinctrl-0 = <&cp0_ge_mdio_pins>; + phy0: ethernet-phy@0 { + status = "okay"; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "ge"; + }; + }; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_spi1 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy0>; + phy-names = "usb"; + /delete-property/ phys; +}; + +&cp0_usb3_1 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy1>; + phy-names = "usb"; + /delete-property/ phys; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi new file mode 100644 index 000000000000..6f3914bcfd01 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the CN9131-DB Com Express CPU module board. + */ + +#include "cn9131-db.dtsi" + +/ { + model = "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board"; + compatible = "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + +}; + +&ap0_reg_sd_vccq { + regulator-max-microvolt = <1800000>; + states = <1800000 0x1 1800000 0x0>; + /delete-property/ gpios; +}; + +&cp0_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_usb3_vbus1 { + /delete-property/ gpio; +}; + +&cp1_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_sd_vcc { + status = "disabled"; +}; + +&cp0_reg_sd_vccq { + status = "disabled"; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_eth0 { + status = "disabled"; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_eth2 { + status = "disabled"; +}; + +&cp0_mdio { + status = "okay"; + pinctrl-0 = <&cp0_ge_mdio_pins>; + phy0: ethernet-phy@0 { + status = "okay"; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "ge"; + }; + }; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_spi1 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy0>; + phy-names = "usb"; + /delete-property/ phys; +}; + +&cp0_usb3_1 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy1>; + phy-names = "usb"; + /delete-property/ phys; +}; + +&cp1_usb3_1 { + status = "okay"; + usb-phy = <&cp1_usb3_0_phy0>; + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy3 1>; + phy-names = "usb"; +};