| Message ID | 20231118123944.2202630-4-quic_skakitap@quicinc.com |
|---|---|
| State | Accepted |
| Commit | 71f130c9193f613d497f7245365ed05ffdb0a401 |
| Headers | show |
| Series | Add runtime PM support for videocc on SM8150 | expand |
diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c index 6a5f89f53da8..52a9a453a143 100644 --- a/drivers/clk/qcom/videocc-sm8150.c +++ b/drivers/clk/qcom/videocc-sm8150.c @@ -33,6 +33,7 @@ static struct alpha_pll_config video_pll0_config = { .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002267, .config_ctl_hi1_val = 0x00000024, + .test_ctl_hi1_val = 0x00000020, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000805, .user_ctl_hi1_val = 0x000000D0,
When the driver was ported upstream, PLL test_ctl_hi1 register value was omitted. Add it to ensure the PLLs are fully configured. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> --- Changes since v1: - Removed updating the test_ctl_hi_val, because as per latest HW recommendation its value is 0x0 which is same as PoR and hence no need to update it. - Keeping test_ctl_hi1_val same as before(v1). drivers/clk/qcom/videocc-sm8150.c | 1 + 1 file changed, 1 insertion(+)