| Message ID | 1700051821-1087-3-git-send-email-quic_msarkar@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: qcom: sa8775p: add cache coherency support for SA8775P | expand |
On Wed, Nov 15, 2023 at 06:07:00PM +0530, Mrinmay Sarkar wrote: > This change will enable cache snooping logic to support > cache coherency for 8775 EP platform. > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Same comment as patch 1/3. - Mani > --- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c > index 3a53d97..ee99fb1 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c > @@ -47,6 +47,7 @@ > #define PARF_DBI_BASE_ADDR_HI 0x354 > #define PARF_SLV_ADDR_SPACE_SIZE 0x358 > #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c > +#define PCIE_PARF_NO_SNOOP_OVERIDE 0x3d4 > #define PARF_ATU_BASE_ADDR 0x634 > #define PARF_ATU_BASE_ADDR_HI 0x638 > #define PARF_SRIS_MODE 0x644 > @@ -86,6 +87,10 @@ > #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) > #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) > > +/* PARF_NO_SNOOP_OVERIDE register fields */ > +#define WR_NO_SNOOP_OVERIDE_EN BIT(1) > +#define RD_NO_SNOOP_OVERIDE_EN BIT(3) > + > /* PARF_DEVICE_TYPE register fields */ > #define PARF_DEVICE_TYPE_EP 0x0 > > @@ -489,6 +494,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) > val |= BIT(8); > writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); > > + /* Enable cache snooping for SA8775P */ > + if (of_device_is_compatible(dev->of_node, "qcom,sa8775p-pcie-ep")) > + writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN, > + pcie_ep->parf + PCIE_PARF_NO_SNOOP_OVERIDE); > + > return 0; > > err_disable_resources: > -- > 2.7.4 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 3a53d97..ee99fb1 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -47,6 +47,7 @@ #define PARF_DBI_BASE_ADDR_HI 0x354 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c +#define PCIE_PARF_NO_SNOOP_OVERIDE 0x3d4 #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 #define PARF_SRIS_MODE 0x644 @@ -86,6 +87,10 @@ #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) +/* PARF_NO_SNOOP_OVERIDE register fields */ +#define WR_NO_SNOOP_OVERIDE_EN BIT(1) +#define RD_NO_SNOOP_OVERIDE_EN BIT(3) + /* PARF_DEVICE_TYPE register fields */ #define PARF_DEVICE_TYPE_EP 0x0 @@ -489,6 +494,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) val |= BIT(8); writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); + /* Enable cache snooping for SA8775P */ + if (of_device_is_compatible(dev->of_node, "qcom,sa8775p-pcie-ep")) + writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN, + pcie_ep->parf + PCIE_PARF_NO_SNOOP_OVERIDE); + return 0; err_disable_resources:
This change will enable cache snooping logic to support cache coherency for 8775 EP platform. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 ++++++++++ 1 file changed, 10 insertions(+)