Message ID | 20231030-ipq5332-nsscc-v1-3-6162a2c65f0a@quicinc.com |
---|---|
State | Superseded |
Headers | show
Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0E5FDF40; Mon, 30 Oct 2023 09:47:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GUPPtWOo" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F68A122; Mon, 30 Oct 2023 02:47:55 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U8JFDq005590; Mon, 30 Oct 2023 09:47:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=47a8Kd/di4nYBiraczXJIoewiBNTXFH+cVUpLiKQv/g=; b=GUPPtWOoFOhxg7/5aka6hFC+4hB9NhOBPI8FAZNYuGr80DygEbGv69bc3Q0m6PVLYtZS +spg9w9pTNqb1b4NtrnwrTBv/vr4CXVR+Ykxv+WnyB47IC9u6b1UKtA2SdwGFi/nnChF M+JQd8s7/2tdECbIPd3qsyO1rQZ2w/dXJgbU3piJedV5gLXiZMHZd+ZpcQ6v0hxFV1/m FbUFl6xr2zr9LFFBBotLLopntc2lcB8XpS1wArk1CQTFzBjpBX8/6BGsmjDlntSIR2a5 AW5KwewhrUR8QTbTlsHvrx25a/aPl9TG0QTKSmHKs1CIPQE1LEFx7pvPD13MhKlhjHsa JQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u0sw7ufpf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:47 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9lkTH027633 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:46 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:47:40 -0700 From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Date: Mon, 30 Oct 2023 15:17:18 +0530 Subject: [PATCH 3/8] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: <devicetree.vger.kernel.org> List-Subscribe: <mailto:devicetree+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:devicetree+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20231030-ipq5332-nsscc-v1-3-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson <andersson@kernel.org>, Andy Gross <agross@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Richard Cochran <richardcochran@gmail.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org> CC: <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <netdev@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, "Kathiravan Thirumoorthy" <quic_kathirav@quicinc.com> X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=721; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=7DHRVV4reBPtWLZAXBh6odJKBZeQj5TFKZRfh5Ysgj4=; b=EqqzTpiqeHfD9K83QVzTIkiN7DZZsPJBmUakXztMM2PE4S5CCmcvK3vi12fYPoG8TAQ6ohwSj 4PVmcel0zdiCqjkRge88icdvIj9IF9S9bGSP7s9nfgpoPQOhLI9Ex5A X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: W3hrVZiwO44iw2X8e9IsJqPIq4TpabnS X-Proofpoint-GUID: W3hrVZiwO44iw2X8e9IsJqPIq4TpabnS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=985 clxscore=1015 phishscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 |
Series |
Add NSS clock controller support for IPQ5332
|
expand
|
diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h index 4649026da332..486b6cf2e916 100644 --- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -176,6 +176,7 @@ #define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 #define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 #define GCC_USB0_PIPE_CLK_SRC 172 +#define GPLL0_OUT_AUX 173 #define GCC_ADSS_BCR 0 #define GCC_ADSS_PWM_CLK_ARES 1
Add the definition for GPLL0_OUT_AUX clock. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> --- include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 + 1 file changed, 1 insertion(+)