Message ID | 20231030-ipq5332-nsscc-v1-8-6162a2c65f0a@quicinc.com |
---|---|
State | Superseded |
Headers | show
Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2D30DDDF; Mon, 30 Oct 2023 09:48:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZInvVHCK" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE6B01A8; Mon, 30 Oct 2023 02:48:23 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U9B7qq021806; Mon, 30 Oct 2023 09:48:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=M6YE6usfdiaDl6y22WzZBuFLQNHUK9IyY63njJBeIiI=; b=ZInvVHCKKd/kwcx+YNztRkt4tRk3raYDjPhB3aXihDZqfs8wx4Fgagf5WuQFAm8tV0IT 70X/I/RczDP3RAXwSrU0cOzghmKtraqKarLqz7rWh4zgKiwYRs3auUZg9ky6Y9+Vckml gVB5+8o+JIYTmZOwJ5eEufwT99BUgMkzvqQLVjRaOVRAjWJhLJm+ZavufD7zYIAeTHbM +u3rIwp3yAR4FsyO2WEIoaS+MLhNNOT1C63LiVtIQQrrzYUaR9A/NAQaRtSckVVNim9p CbJDzCQcNmNH9D95RKbk6F/e9nrbo4In25I0WFycX8c+ASzYnZ9QZGE+l1Sn5qMRwhIl pQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u0u2qkaqc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:48:15 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9mEFi017824 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:48:14 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:48:08 -0700 From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Date: Mon, 30 Oct 2023 15:17:23 +0530 Subject: [PATCH 8/8] arm64: defconfig: build NSS Clock Controller driver for IPQ5332 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: <devicetree.vger.kernel.org> List-Subscribe: <mailto:devicetree+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:devicetree+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20231030-ipq5332-nsscc-v1-8-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson <andersson@kernel.org>, Andy Gross <agross@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Richard Cochran <richardcochran@gmail.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org> CC: <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <netdev@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, "Kathiravan Thirumoorthy" <quic_kathirav@quicinc.com> X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=619; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=Ka2Puxp6GzvfCF+k1mTawKzWStf8whNbVMFFBPTF228=; b=i3HBsZuuL8VZD8ySQ4Ban1f5nOJsZ06tXSn6krN9Gd7P7+mqEAYzZX+NA3fBJffI4TY2phlw7 HDqkMoN9Px/DYTEQdbyZR5a+3rWVFARbx0aNvuBsq9I4wy5/KQ8b2+S X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 1Aw7B_IO2BhtIDyVc4vsUH20pVBjkOv2 X-Proofpoint-GUID: 1Aw7B_IO2BhtIDyVc4vsUH20pVBjkOv2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxlogscore=685 priorityscore=1501 bulkscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 |
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Add NSS clock controller support for IPQ5332
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expand
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diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b60aa1f89343..c075202d255d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1223,6 +1223,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_GCC_5332=y +CONFIG_IPQ_NSSCC_5332=m CONFIG_IPQ_APSS_5018=y CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_6018=y
Build Qualcomm IPQ9574 NSSCC driver as module. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)