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[PULL,08/41] target/arm: Move ID_AA64DFR* feature tests together

Message ID 20231027143942.3413881-9-peter.maydell@linaro.org
State Accepted
Commit 1036ce4e6a2fa0f865e2e6514d198db931b5510f
Headers show
Series [PULL,01/41] target/arm: Correct minor errors in Cortex-A710 definition | expand

Commit Message

Peter Maydell Oct. 27, 2023, 2:39 p.m. UTC 
Move all the ID_AA64DFR* feature test functions together.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231024163510.2972081-7-peter.maydell@linaro.org
---
 target/arm/cpu-features.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
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Patch

diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 0ed05b8b19e..66212cd7ecc 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -857,6 +857,11 @@  static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
 }
 
+static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
+{
+    return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
+}
+
 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
@@ -922,11 +927,6 @@  static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
 }
 
-static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
-{
-    return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
-}
-
 /*
  * Feature tests for "does this exist in either 32-bit or 64-bit?"
  */