@@ -273,6 +273,17 @@ int acpi_get_imsic_mmio_info(u32 index, struct resource *res)
return 0;
}
+static struct fwnode_handle *riscv_get_gsi_domain_id(u32 gsi)
+{
+ struct fwnode_handle *gsi_fwnode = NULL;
+
+ gsi_fwnode = aplic_get_gsi_domain_id(gsi);
+ if (!gsi_fwnode)
+ gsi_fwnode = plic_get_gsi_domain_id(gsi);
+
+ return gsi_fwnode;
+}
+
static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
const unsigned long end)
{
@@ -318,6 +329,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
* unsupported. Once IMSIC is probed, MSI support will be set.
*/
pci_no_msi();
+ acpi_set_irq_model(ACPI_IRQ_MODEL_RINTC, riscv_get_gsi_domain_id);
return 0;
}
INTC being the root interrupt controller, set the ACPI irqmodel with callback function to get the GSI domain id. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> --- drivers/irqchip/irq-riscv-intc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)