diff mbox series

[PULL,05/94] configs: Enable MTTCG for sparc, sparc64

Message ID	20231026001542.1141412-10-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Subject: [PULL 05/94] configs: Enable MTTCG for sparc, sparc64 Date: Wed, 25 Oct 2023 17:13:48 -0700 Message-Id: <20231026001542.1141412-10-richard.henderson@linaro.org> In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/94] target/sparc: Clear may_lookup for npc == DYNAMIC_PC \| expand [PULL,01/94] target/sparc: Clear may_lookup for npc == DYNAMIC_PC [PULL,02/94] target/sparc: Implement check_align inline [03/29] tcg/optimize: Split out do_constant_folding_cond1 [PULL,04/94] target/sparc: Set TCG_GUEST_DEFAULT_MO [PULL,05/94] configs: Enable MTTCG for sparc, sparc64 [06/29] tcg/optimize: Handle TCG_COND_TST{EQ,NE} [07/29] tcg/aarch64: Support TCG_COND_TST{EQ,NE} [08/29] tcg/aarch64: Generate TBZ, TBNZ [PULL,09/94] target/sparc: Partition cpu features [10/29] tcg/i386: Pass x86 condition codes to tcg_out_cmov [11/29] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp [12/29] tcg/i386: Add rexw argument to tcg_out_testi [13/29] tcg/i386: Support TCG_COND_TST{EQ,NE} [PULL,14/94] target/sparc: Move BPr to decodetree [15/29] tcg/mips: Support TCG_COND_TST{EQ,NE} [16/29] tcg/riscv: Support TCG_COND_TST{EQ,NE} [PULL,17/94] target/sparc: Merge gen_fcond with only caller [18/29] tcg/sparc64: Hoist read of tcg_cond_to_rcond [19/29] tcg/sparc64: Pass TCGCond to tcg_out_cmp [PULL,20/94] target/sparc: Move SETHI to decodetree [PULL,21/94] target/sparc: Move Tcc to decodetree [PULL,22/94] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree [PULL,23/94] target/sparc: Move RDPSR, RDHPR to decodetree [PULL,24/94] target/sparc: Move RDWIM, RDPR to decodetree [PULL,25/94] target/sparc: Move RDTBR, FLUSHW to decodetree [PULL,26/94] target/sparc: Move WRASR to decodetree [27/29] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} [28/29] target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S} [29/29] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero [PULL,30/94] target/sparc: Remove cpu_wim [PULL,31/94] target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr [PULL,32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver [PULL,33/94] target/sparc: Move basic arithmetic to decodetree [PULL,34/94] target/sparc: Move ADDC to decodetree [PULL,35/94] target/sparc: Move MULX to decodetree [PULL,36/94] target/sparc: Move UMUL, SMUL to decodetree [PULL,37/94] target/sparc: Move SUBC to decodetree [PULL,38/94] target/sparc: Move UDIVX, SDIVX to decodetree [PULL,39/94] target/sparc: Move UDIV, SDIV to decodetree [PULL,40/94] target/sparc: Move TADD, TSUB, MULS to decodetree [PULL,41/94] target/sparc: Move SLL, SRL, SRA to decodetree [PULL,42/94] target/sparc: Move MOVcc, MOVR to decodetree [PULL,43/94] target/sparc: Move POPC to decodetree [PULL,44/94] target/sparc: Convert remaining v8 coproc insns to decodetree [PULL,45/94] target/sparc: Move JMPL, RETT, RETURN to decodetree [PULL,46/94] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree [PULL,47/94] target/sparc: Move DONE, RETRY to decodetree [PULL,48/94] target/sparc: Split out resolve_asi [PULL,49/94] target/sparc: Drop ifdef around get_asi and friends [PULL,50/94] target/sparc: Split out ldst functions with asi pre-computed [PULL,51/94] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX [PULL,52/94] target/sparc: Move simple integer load/store to decodetree [PULL,53/94] target/sparc: Move asi integer load/store to decodetree [PULL,54/94] target/sparc: Move LDSTUB, LDSTUBA to decodetree [PULL,55/94] target/sparc: Move SWAP, SWAPA to decodetree [PULL,56/94] target/sparc: Move CASA, CASXA to decodetree [PULL,57/94] target/sparc: Move PREFETCH, PREFETCHA to decodetree [PULL,58/94] target/sparc: Split out fp ldst functions with asi precomputed [PULL,59/94] target/sparc: Move simple fp load/store to decodetree [PULL,60/94] target/sparc: Move asi fp load/store to decodetree [PULL,61/94] target/sparc: Move LDFSR, STFSR to decodetree [PULL,62/94] target/sparc: Merge LDFSR, LDXFSR implementations [PULL,63/94] target/sparc: Move EDGE* to decodetree [PULL,64/94] target/sparc: Move ARRAY* to decodetree [PULL,65/94] target/sparc: Move ADDRALIGN* to decodetree [PULL,66/94] target/sparc: Move BMASK to decodetree [PULL,67/94] target/sparc: Move FMOVS, FNEGS, FABSS, FSRCS, FNOTS to decodetree [PULL,68/94] target/sparc: Move FMOVD, FNEGD, FABSD, FSRCD, FNOTD to decodetree [PULL,69/94] target/sparc: Use tcg_gen_vec_{add,sub}* [PULL,70/94] target/sparc: Move gen_ne_fop_FFF insns to decodetree [PULL,71/94] target/sparc: Move gen_ne_fop_DDD insns to decodetree [PULL,72/94] target/sparc: Move PDIST to decodetree [PULL,73/94] target/sparc: Move gen_gsr_fop_DDD insns to decodetree [PULL,74/94] target/sparc: Move gen_fop_FF insns to decodetree [PULL,75/94] target/sparc: Move gen_fop_DD insns to decodetree [PULL,76/94] target/sparc: Move FSQRTq to decodetree [PULL,77/94] target/sparc: Move gen_fop_FFF insns to decodetree [PULL,78/94] target/sparc: Move gen_fop_DDD insns to decodetree [PULL,79/94] target/sparc: Move gen_fop_QQQ insns to decodetree [PULL,80/94] target/sparc: Move FSMULD to decodetree [PULL,81/94] target/sparc: Move FDMULQ to decodetree [PULL,82/94] target/sparc: Move gen_fop_FD insns to decodetree [PULL,83/94] target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree [PULL,84/94] target/sparc: Move FqTOs, FqTOi to decodetree [PULL,85/94] target/sparc: Move FqTOd, FqTOx to decodetree [PULL,86/94] target/sparc: Move FiTOq, FsTOq to decodetree [PULL,87/94] target/sparc: Move FdTOq, FxTOq to decodetree [PULL,88/94] target/sparc: Move FMOVq, FNEGq, FABSq to decodetree [PULL,89/94] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree [PULL,90/94] target/sparc: Convert FCMP, FCMPE to decodetree [PULL,91/94] target/sparc: Move FPCMP* to decodetree [PULL,92/94] target/sparc: Move FPACK16, FPACKFIX to decodetree [PULL,93/94] target/sparc: Convert FZERO, FONE to decodetree [PULL,94/94] target/sparc: Remove disas_sparc_legacy

Commit Message

Richard Henderson Oct. 26, 2023, 12:13 a.m. UTC

This will be of small comfort to sparc64, because both
sun4u and sun4v board models force max_cpus = 1.
But it does enable actual smp for sparc32 sun4m.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configs/targets/sparc-softmmu.mak   | 1 +
 configs/targets/sparc64-softmmu.mak | 1 +
 2 files changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak
index 454eb35499..a5d9200382 100644
--- a/configs/targets/sparc-softmmu.mak
+++ b/configs/targets/sparc-softmmu.mak
@@ -1,2 +1,3 @@ 
 TARGET_ARCH=sparc
 TARGET_BIG_ENDIAN=y
+TARGET_SUPPORTS_MTTCG=y
diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
index d3f8a3b710..36ca64ec41 100644
--- a/configs/targets/sparc64-softmmu.mak
+++ b/configs/targets/sparc64-softmmu.mak
@@ -1,3 +1,4 @@ 
 TARGET_ARCH=sparc64
 TARGET_BASE_ARCH=sparc
 TARGET_BIG_ENDIAN=y
+TARGET_SUPPORTS_MTTCG=y