| Message ID | 20231020072140.900967-8-apatel@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3,1/9] RISC-V: Add defines for SBI debug console extension | expand |
On Sat, Oct 21, 2023 at 10:16 PM Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote: > > On Fri, Oct 20, 2023 at 12:51:38PM +0530, Anup Patel wrote: > > We extend the existing RISC-V SBI earlycon support to use the new > > RISC-V SBI debug console extension. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > > --- > > drivers/tty/serial/Kconfig | 2 +- > > drivers/tty/serial/earlycon-riscv-sbi.c | 32 +++++++++++++++++++++---- > > 2 files changed, 29 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig > > index bdc568a4ab66..cec46091a716 100644 > > --- a/drivers/tty/serial/Kconfig > > +++ b/drivers/tty/serial/Kconfig > > @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST > > > > config SERIAL_EARLYCON_RISCV_SBI > > bool "Early console using RISC-V SBI" > > - depends on RISCV_SBI_V01 > > + depends on RISCV_SBI > > select SERIAL_CORE > > select SERIAL_CORE_CONSOLE > > select SERIAL_EARLYCON > > diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/earlycon-riscv-sbi.c > > index 27afb0b74ea7..c21cdef254e7 100644 > > --- a/drivers/tty/serial/earlycon-riscv-sbi.c > > +++ b/drivers/tty/serial/earlycon-riscv-sbi.c > > @@ -15,17 +15,41 @@ static void sbi_putc(struct uart_port *port, unsigned char c) > > sbi_console_putchar(c); > > } > > > > -static void sbi_console_write(struct console *con, > > - const char *s, unsigned n) > > +static void sbi_0_1_console_write(struct console *con, > > + const char *s, unsigned int n) > > { > > struct earlycon_device *dev = con->data; > > uart_console_write(&dev->port, s, n, sbi_putc); > > } > > > > +static void sbi_dbcn_console_write(struct console *con, > > + const char *s, unsigned int n) > > +{ > > + phys_addr_t pa = __pa(s); > > + > > + if (IS_ENABLED(CONFIG_32BIT)) > > + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, > > + n, lower_32_bits(pa), upper_32_bits(pa), 0, 0, 0); > > + else > > + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, > > + n, pa, 0, 0, 0, 0); > > This is still a bit hard to follow, and I guarantee it will be a pain to > maintain over time, trying to keep both calls in sync, right? > > Why not fix up sbi_ecall() to get this correct instead? It should be > handling phys_addr_t values, not forcing you to do odd bit masking every > single time you call it, right? That would make things much easier > overall, and this patch simpler, as well as the next one. On RV32 systems, the physical address can be 34bits wide hence the on RV32 we have to pass physical address as two parameters whereas on RV64 entier physical address can be passed as single parameter. > > Oh wait, sbi_ecall() is crazy, and just a pass-through, so that's not > going to work, you need a wrapper function for this mess to do that bit > twiddeling for you instead of forcing you to do it each time, I guess > that's what you are trying to do here, but ick, is it correct? Yes, it is better to have a wrapper function to hide the differences of RV32 and RV64 systems. I will update. > > thanks, > > greg k-h > > -- > kvm-riscv mailing list > kvm-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv Regards, Anup
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index bdc568a4ab66..cec46091a716 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/earlycon-riscv-sbi.c index 27afb0b74ea7..c21cdef254e7 100644 --- a/drivers/tty/serial/earlycon-riscv-sbi.c +++ b/drivers/tty/serial/earlycon-riscv-sbi.c @@ -15,17 +15,41 @@ static void sbi_putc(struct uart_port *port, unsigned char c) sbi_console_putchar(c); } -static void sbi_console_write(struct console *con, - const char *s, unsigned n) +static void sbi_0_1_console_write(struct console *con, + const char *s, unsigned int n) { struct earlycon_device *dev = con->data; uart_console_write(&dev->port, s, n, sbi_putc); } +static void sbi_dbcn_console_write(struct console *con, + const char *s, unsigned int n) +{ + phys_addr_t pa = __pa(s); + + if (IS_ENABLED(CONFIG_32BIT)) + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + n, lower_32_bits(pa), upper_32_bits(pa), 0, 0, 0); + else + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + n, pa, 0, 0, 0, 0); +} + static int __init early_sbi_setup(struct earlycon_device *device, const char *opt) { - device->con->write = sbi_console_write; - return 0; + int ret = 0; + + if ((sbi_spec_version >= sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { + device->con->write = sbi_dbcn_console_write; + } else { + if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) + device->con->write = sbi_0_1_console_write; + else + ret = -ENODEV; + } + + return ret; } EARLYCON_DECLARE(sbi, early_sbi_setup);