diff mbox series

[v2,06/65] target/hppa: Fix hppa64 case in machine.c

Message ID	20231020204331.139847-7-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 06/65] target/hppa: Fix hppa64 case in machine.c Date: Fri, 20 Oct 2023 13:42:32 -0700 Message-Id: <20231020204331.139847-7-richard.henderson@linaro.org> In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/hppa: Implement hppa64-cpu \| expand [v2,00/65] target/hppa: Implement hppa64-cpu [v2,01/65] tcg: Improve expansion of deposit of constant [v2,02/65] tcg: Improve expansion of deposit into a constant [v2,03/65] target/hppa: Remove get_temp [v2,04/65] target/hppa: Remove get_temp_tl [v2,05/65] target/hppa: Remove load_const [v2,06/65] target/hppa: Fix hppa64 case in machine.c [v2,07/65] target/hppa: Fix load in do_load_32 [v2,08/65] target/hppa: Truncate rotate count in trans_shrpw_sar [v2,09/65] target/hppa: Fix trans_ds for hppa64 [v2,10/65] target/hppa: Fix do_add, do_sub for hppa64 [v2,11/65] target/hppa: Fix bb_sar for hppa64 [v2,12/65] target/hppa: Fix extrw and depw with sar for hppa64 [v2,13/65] target/hppa: Introduce TYPE_HPPA64_CPU [v2,14/65] target/hppa: Make HPPA_BTLB_ENTRIES variable [v2,15/65] target/hppa: Implement cpu_list [v2,16/65] target/hppa: Implement hppa_cpu_class_by_name [v2,17/65] target/hppa: Update cpu_hppa_get/put_psw for hppa64 [v2,18/65] target/hppa: Handle absolute addresses for pa2.0 [v2,19/65] target/hppa: Adjust hppa_cpu_dump_state for hppa64 [v2,20/65] target/hppa: Fix hppa64 addressing [v2,21/65] target/hppa: sar register allows only 5 bits on 32-bit CPU [v2,22/65] target/hppa: Pass d to do_cond [v2,23/65] target/hppa: Pass d to do_sub_cond [v2,24/65] target/hppa: Pass d to do_log_cond [v2,25/65] target/hppa: Pass d to do_sed_cond [v2,26/65] target/hppa: Pass d to do_unit_cond [v2,27/65] linux-user/hppa: Fixes for TARGET_ABI32 [v2,28/65] target/hppa: Drop attempted gdbstub support for hppa64 [v2,29/65] target/hppa: Remove TARGET_HPPA64 [v2,30/65] target/hppa: Decode d for logical instructions [v2,31/65] target/hppa: Decode d for unit instructions [v2,32/65] target/hppa: Decode d for cmpclr instructions [v2,33/65] target/hppa: Decode d for add instructions [v2,34/65] target/hppa: Decode d for sub instructions [v2,35/65] target/hppa: Decode d for bb instructions [v2,36/65] target/hppa: Decode d for cmpb instructions [v2,37/65] target/hppa: Decode CMPIB double-word [v2,38/65] target/hppa: Decode ADDB double-word [v2,39/65] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA [v2,40/65] target/hppa: Implement DEPD, DEPDI [v2,41/65] target/hppa: Implement EXTRD [v2,42/65] target/hppa: Implement SHRPD [v2,43/65] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM [v2,44/65] target/hppa: Implement STDBY [v2,45/65] target/hppa: Implement IDTLBT, IITLBT [v2,46/65] hw/hppa: Use uint32_t instead of target_ureg [v2,47/65] target/hppa: Remove TARGET_REGISTER_BITS [v2,48/65] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections [v2,49/65] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections [v2,50/65] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new [v2,51/65] target/hppa: Replace tcg_gen__tl with tcg_gen__i64 [v2,52/65] target/hppa: Implement HADD [v2,53/65] target/hppa: Implement HSUB [v2,54/65] target/hppa: Implement HAVG [v2,55/65] target/hppa: Implement HSHL, HSHR [v2,56/65] target/hppa: Implement HSHLADD, HSHRADD [v2,57/65] target/hppa: Implement MIXH, MIXW [v2,58/65] target/hppa: Implement PERMH [v2,59/65] target/hppa: Fix interruption based on default PSW [v2,60/65] target/hppa: Precompute zero into DisasContext [v2,61/65] target/hppa: Return zero for r0 from load_gpr [v2,62/65] target/hppa: Simplify trans_dep*_imm [v2,63/65] include/hw/elf: Remove truncating signed casts [v2,64/65] hw/hppa: Translate phys addresses for the cpu [v2,65/65] linux-user/hppa: Drop EXCP_DUMP from handled exceptions

Commit Message

Richard Henderson Oct. 20, 2023, 8:42 p.m. UTC

Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/machine.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/target/hppa/machine.c b/target/hppa/machine.c
index 905991d7f9..0c0bba68c0 100644
--- a/target/hppa/machine.c
+++ b/target/hppa/machine.c
@@ -24,9 +24,9 @@ 
 #if TARGET_REGISTER_BITS == 64
 #define qemu_put_betr   qemu_put_be64
 #define qemu_get_betr   qemu_get_be64
-#define VMSTATE_UINTTL_V(_f, _s, _v) \
+#define VMSTATE_UINTTR_V(_f, _s, _v) \
     VMSTATE_UINT64_V(_f, _s, _v)
-#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
+#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \
     VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
 #else
 #define qemu_put_betr   qemu_put_be32