@@ -284,6 +284,9 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
return hppa_form_gva_psw(env->psw, spc, off);
}
+hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr);
+hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);
+
/*
* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
* TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
@@ -109,8 +109,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
cb |= ((psw >> 8) & 1) << 4;
env->psw_cb = cb;
- /* If PSW_P changes, it affects how we translate addresses. */
- if ((psw ^ old_psw) & PSW_P) {
+ /* If P or W changes, it affects how we translate addresses. */
+ if ((psw ^ old_psw) & (PSW_P | PSW_W)) {
#ifndef CONFIG_USER_ONLY
tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
#endif
@@ -25,6 +25,45 @@
#include "hw/core/cpu.h"
#include "trace.h"
+hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr)
+{
+ if (likely(extract64(addr, 58, 4) != 0xf)) {
+ /* Memory address space */
+ return addr & MAKE_64BIT_MASK(0, 62);
+ }
+ if (extract64(addr, 54, 4) != 0) {
+ /* I/O address space */
+ return addr | MAKE_64BIT_MASK(62, 2);
+ }
+ /* PDC address space */
+ return (addr & MAKE_64BIT_MASK(0, 54)) | MAKE_64BIT_MASK(60, 4);
+}
+
+hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr)
+{
+ if (likely(extract32(addr, 28, 4) != 0xf)) {
+ /* Memory address space */
+ return addr & MAKE_64BIT_MASK(0, 32);
+ }
+ if (extract32(addr, 24, 4) != 0) {
+ /* I/O address space */
+ return addr | MAKE_64BIT_MASK(32, 32);
+ }
+ /* PDC address space */
+ return (addr & MAKE_64BIT_MASK(0, 24)) | MAKE_64BIT_MASK(60, 4);
+}
+
+static hwaddr hppa_abs_to_phys(CPUHPPAState *env, vaddr addr)
+{
+ if (!hppa_is_pa20(env)) {
+ return addr;
+ } else if (env->psw & PSW_W) {
+ return hppa_abs_to_phys_pa2_w1(addr);
+ } else {
+ return hppa_abs_to_phys_pa2_w0(addr);
+ }
+}
+
static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
{
int i;
@@ -99,7 +138,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
/* Virtual translation disabled. Direct map virtual to physical. */
if (mmu_idx == MMU_PHYS_IDX) {
- phys = addr;
+ phys = hppa_abs_to_phys(env, addr);
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
goto egress;
}
@@ -213,7 +252,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
/* ??? We really ought to know if the code mmu is disabled too,
in order to get the correct debugging dumps. */
if (!(cpu->env.psw & PSW_D)) {
- return addr;
+ return hppa_abs_to_phys(&cpu->env, addr);
}
excp = hppa_get_physical_address(&cpu->env, addr, MMU_KERNEL_IDX, 0,
@@ -299,7 +338,11 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
/* Note that empty->entry_valid == 0 already. */
empty->va_b = addr & TARGET_PAGE_MASK;
empty->va_e = empty->va_b + TARGET_PAGE_SIZE - 1;
- empty->pa = extract32(reg, 5, 20) << TARGET_PAGE_BITS;
+ /*
+ * FIXME: This is wrong, as this is a pa1.1 function.
+ * But for the moment translate abs address for pa2.0.
+ */
+ empty->pa = hppa_abs_to_phys(env, extract32(reg, 5, 20) << TARGET_PAGE_BITS);
trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa);
}
@@ -71,6 +71,15 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
* so let this go without comment.
*/
env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM);
+
+ /*
+ * Changes to PSW_W change the translation of absolute to physical.
+ * This currently (incorrectly) affects all translations.
+ */
+ if ((psw ^ env->psw) & (PSW_P | PSW_W)) {
+ tlb_flush(env_cpu(env));
+ }
+
return psw & PSW_SM;
}
With pa2.0, absolute addresses are not the same as physical addresses, and undergo a transformation based on PSW_W. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/hppa/cpu.h | 3 +++ target/hppa/helper.c | 4 ++-- target/hppa/mem_helper.c | 49 +++++++++++++++++++++++++++++++++++++--- target/hppa/sys_helper.c | 9 ++++++++ 4 files changed, 60 insertions(+), 5 deletions(-)