| Message ID | 20231016064934.1913964-5-schalla@marvell.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Marvell CN10KB/CN10KA B0 support | expand |
Hi Srujana, kernel test robot noticed the following build errors: [auto build test ERROR on herbert-cryptodev-2.6/master] [also build test ERROR on herbert-crypto-2.6/master linus/master v6.6-rc6 next-20231020] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Srujana-Challa/crypto-octeontx2-remove-CPT-block-reset/20231017-141612 base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master patch link: https://lore.kernel.org/r/20231016064934.1913964-5-schalla%40marvell.com patch subject: [PATCH 04/10] crypto: octeontx2: add devlink option to set t106 mode config: loongarch-allmodconfig (https://download.01.org/0day-ci/archive/20231021/202310211716.02lrxOQo-lkp@intel.com/config) compiler: loongarch64-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231021/202310211716.02lrxOQo-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202310211716.02lrxOQo-lkp@intel.com/ All errors (new ones prefixed by >>): drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c: In function 'otx2_cpt_register_dl': >> drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c:208:9: error: implicit declaration of function 'devlink_params_publish'; did you mean 'devlink_params_register'? [-Werror=implicit-function-declaration] 208 | devlink_params_publish(dl); | ^~~~~~~~~~~~~~~~~~~~~~ | devlink_params_register cc1: some warnings being treated as errors vim +208 drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c 181 182 int otx2_cpt_register_dl(struct otx2_cptpf_dev *cptpf) 183 { 184 struct device *dev = &cptpf->pdev->dev; 185 struct otx2_cpt_devlink *cpt_dl; 186 struct devlink *dl; 187 int ret; 188 189 dl = devlink_alloc(&otx2_cpt_devlink_ops, 190 sizeof(struct otx2_cpt_devlink), dev); 191 if (!dl) { 192 dev_warn(dev, "devlink_alloc failed\n"); 193 return -ENOMEM; 194 } 195 196 cpt_dl = devlink_priv(dl); 197 cpt_dl->dl = dl; 198 cpt_dl->cptpf = cptpf; 199 cptpf->dl = dl; 200 ret = devlink_params_register(dl, otx2_cpt_dl_params, 201 ARRAY_SIZE(otx2_cpt_dl_params)); 202 if (ret) { 203 dev_err(dev, "devlink params register failed with error %d", 204 ret); 205 devlink_free(dl); 206 return ret; 207 } > 208 devlink_params_publish(dl); 209 devlink_register(dl); 210 211 return 0; 212 } 213
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h index 805b2adf0c22..bef78db15a89 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h @@ -200,6 +200,14 @@ static inline bool cpt_feature_rxc_icb_cnt(struct pci_dev *pdev) return false; } +static inline bool cpt_feature_sgv2(struct pci_dev *pdev) +{ + if (!is_dev_otx2(pdev) && !is_dev_cn10ka_ax(pdev)) + return true; + + return false; +} + int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev); int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev); diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c b/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c index e11f334600c7..161eeb54c306 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c @@ -24,10 +24,7 @@ static int otx2_cpt_dl_egrp_delete(struct devlink *dl, u32 id, static int otx2_cpt_dl_uc_info(struct devlink *dl, u32 id, struct devlink_param_gset_ctx *ctx) { - struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl); - struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf; - - otx2_cpt_print_uc_dbg_info(cptpf); + ctx->val.vstr[0] = '\0'; return 0; } @@ -69,11 +66,50 @@ static int otx2_cpt_dl_max_rxc_icb_cnt_set(struct devlink *dl, u32 id, return 0; } +static int otx2_cpt_dl_t106_mode_get(struct devlink *dl, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl); + struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf; + struct pci_dev *pdev = cptpf->pdev; + u64 reg_val = 0; + + otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_val, + BLKADDR_CPT0); + ctx->val.vu8 = (reg_val >> 18) & 0x1; + + return 0; +} + +static int otx2_cpt_dl_t106_mode_set(struct devlink *dl, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl); + struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf; + struct pci_dev *pdev = cptpf->pdev; + u64 reg_val = 0; + + if (cptpf->enabled_vfs != 0 || cptpf->eng_grps.is_grps_created) + return -EPERM; + + if (cpt_feature_sgv2(pdev)) { + otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_val, + BLKADDR_CPT0); + reg_val &= ~(0x1ULL << 18); + reg_val |= ((u64)ctx->val.vu8 & 0x1) << 18; + return otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, + reg_val, BLKADDR_CPT0); + } + + return 0; +} + enum otx2_cpt_dl_param_id { OTX2_CPT_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, OTX2_CPT_DEVLINK_PARAM_ID_EGRP_CREATE, OTX2_CPT_DEVLINK_PARAM_ID_EGRP_DELETE, OTX2_CPT_DEVLINK_PARAM_ID_MAX_RXC_ICB_CNT, + OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE, }; static const struct devlink_param otx2_cpt_dl_params[] = { @@ -93,6 +129,11 @@ static const struct devlink_param otx2_cpt_dl_params[] = { otx2_cpt_dl_max_rxc_icb_cnt, otx2_cpt_dl_max_rxc_icb_cnt_set, NULL), + DEVLINK_PARAM_DRIVER(OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE, + "t106_mode", DEVLINK_PARAM_TYPE_U8, + BIT(DEVLINK_PARAM_CMODE_RUNTIME), + otx2_cpt_dl_t106_mode_get, otx2_cpt_dl_t106_mode_set, + NULL), }; static int otx2_cpt_dl_info_firmware_version_put(struct devlink_info_req *req, @@ -164,7 +205,7 @@ int otx2_cpt_register_dl(struct otx2_cptpf_dev *cptpf) devlink_free(dl); return ret; } - + devlink_params_publish(dl); devlink_register(dl); return 0; diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c index c64c50a964ed..7d44b54659bf 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c @@ -600,10 +600,10 @@ static int cptpf_get_rid(struct pci_dev *pdev, struct otx2_cptpf_dev *cptpf) } otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_val, BLKADDR_CPT0); - if ((is_dev_cn10ka_b0(pdev) && (reg_val & BIT_ULL(18))) || + if ((cpt_feature_sgv2(pdev) && (reg_val & BIT_ULL(18))) || is_dev_cn10ka_ax(pdev)) eng_grps->rid = CPT_UC_RID_CN10K_A; - else if (is_dev_cn10kb(pdev) || is_dev_cn10ka_b0(pdev)) + else if (cpt_feature_sgv2(pdev)) eng_grps->rid = CPT_UC_RID_CN10K_B; return 0;
On CN10KA B0/CN10KB, CPT scatter gather format has modified to support multi-seg in inline IPsec. Due to this CPT requires new firmware and doesn't work with CN10KA0/A1 firmware. To make HW works in backward compatibility mode or works with CN10KA0/A1 firmware, a bit(T106_MODE) is introduced in HW CSR. This patch adds devlink parameter for configuring T106_MODE. Signed-off-by: Srujana Challa <schalla@marvell.com> --- .../marvell/octeontx2/otx2_cpt_common.h | 8 +++ .../marvell/octeontx2/otx2_cpt_devlink.c | 51 +++++++++++++++++-- .../marvell/octeontx2/otx2_cptpf_main.c | 4 +- 3 files changed, 56 insertions(+), 7 deletions(-)