| Message ID | 20231013140116.255-14-philmd@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target: Make 'cpu-qom.h' really target agnostic | expand |
On Fri, Oct 13, 2023 at 04:01:12PM +0200, Philippe Mathieu-Daudé wrote: > Date: Fri, 13 Oct 2023 16:01:12 +0200 > From: Philippe Mathieu-Daudé <philmd@linaro.org> > Subject: [PATCH v2 13/16] target/i386: Declare CPU QOM types using > DEFINE_TYPES() macro > X-Mailer: git-send-email 2.41.0 > > When multiple QOM types are registered in the same file, > it is simpler to use the the DEFINE_TYPES() macro. In > particular because type array declared with such macro > are easier to review. > > In few commits we are going to add more types, so replace > the type_register_static() to ease further reviews. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/i386/cpu.c | 50 ++++++++++++++++++++++------------------------- > 1 file changed, 23 insertions(+), 27 deletions(-) Reviewed-by: Zhao Liu <zhao1.liu@intel.com> > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 3aab05ddad..81b05d421c 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -4990,13 +4990,6 @@ static void max_x86_cpu_initfn(Object *obj) > &error_abort); > } > > -static const TypeInfo max_x86_cpu_type_info = { > - .name = X86_CPU_TYPE_NAME("max"), > - .parent = TYPE_X86_CPU, > - .instance_init = max_x86_cpu_initfn, > - .class_init = max_x86_cpu_class_init, > -}; > - > static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) > { > assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); > @@ -8018,19 +8011,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) > } > } > > -static const TypeInfo x86_cpu_type_info = { > - .name = TYPE_X86_CPU, > - .parent = TYPE_CPU, > - .instance_size = sizeof(X86CPU), > - .instance_align = __alignof(X86CPU), > - .instance_init = x86_cpu_initfn, > - .instance_post_init = x86_cpu_post_initfn, > - > - .abstract = true, > - .class_size = sizeof(X86CPUClass), > - .class_init = x86_cpu_common_class_init, > -}; > - > /* "base" CPU model, used by query-cpu-model-expansion */ > static void x86_cpu_base_class_init(ObjectClass *oc, void *data) > { > @@ -8042,22 +8022,38 @@ static void x86_cpu_base_class_init(ObjectClass *oc, void *data) > xcc->ordering = 8; > } > > -static const TypeInfo x86_base_cpu_type_info = { > - .name = X86_CPU_TYPE_NAME("base"), > - .parent = TYPE_X86_CPU, > - .class_init = x86_cpu_base_class_init, > +static const TypeInfo x86_cpu_types[] = { > + { > + .name = TYPE_X86_CPU, > + .parent = TYPE_CPU, > + .abstract = true, > + .instance_size = sizeof(X86CPU), > + .instance_align = __alignof(X86CPU), > + .instance_init = x86_cpu_initfn, > + .instance_post_init = x86_cpu_post_initfn, > + .class_size = sizeof(X86CPUClass), > + .class_init = x86_cpu_common_class_init, > + }, { > + .name = X86_CPU_TYPE_NAME("base"), > + .parent = TYPE_X86_CPU, > + .class_init = x86_cpu_base_class_init, > + }, { > + .name = X86_CPU_TYPE_NAME("max"), > + .parent = TYPE_X86_CPU, > + .instance_init = max_x86_cpu_initfn, > + .class_init = max_x86_cpu_class_init, > + } > }; > > +DEFINE_TYPES(x86_cpu_types) > + > static void x86_cpu_register_types(void) > { > int i; > > - type_register_static(&x86_cpu_type_info); > for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { > x86_register_cpudef_types(&builtin_x86_defs[i]); > } > - type_register_static(&max_x86_cpu_type_info); > - type_register_static(&x86_base_cpu_type_info); > } > > type_init(x86_cpu_register_types) > -- > 2.41.0 > > >
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3aab05ddad..81b05d421c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4990,13 +4990,6 @@ static void max_x86_cpu_initfn(Object *obj) &error_abort); } -static const TypeInfo max_x86_cpu_type_info = { - .name = X86_CPU_TYPE_NAME("max"), - .parent = TYPE_X86_CPU, - .instance_init = max_x86_cpu_initfn, - .class_init = max_x86_cpu_class_init, -}; - static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) { assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); @@ -8018,19 +8011,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) } } -static const TypeInfo x86_cpu_type_info = { - .name = TYPE_X86_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(X86CPU), - .instance_align = __alignof(X86CPU), - .instance_init = x86_cpu_initfn, - .instance_post_init = x86_cpu_post_initfn, - - .abstract = true, - .class_size = sizeof(X86CPUClass), - .class_init = x86_cpu_common_class_init, -}; - /* "base" CPU model, used by query-cpu-model-expansion */ static void x86_cpu_base_class_init(ObjectClass *oc, void *data) { @@ -8042,22 +8022,38 @@ static void x86_cpu_base_class_init(ObjectClass *oc, void *data) xcc->ordering = 8; } -static const TypeInfo x86_base_cpu_type_info = { - .name = X86_CPU_TYPE_NAME("base"), - .parent = TYPE_X86_CPU, - .class_init = x86_cpu_base_class_init, +static const TypeInfo x86_cpu_types[] = { + { + .name = TYPE_X86_CPU, + .parent = TYPE_CPU, + .abstract = true, + .instance_size = sizeof(X86CPU), + .instance_align = __alignof(X86CPU), + .instance_init = x86_cpu_initfn, + .instance_post_init = x86_cpu_post_initfn, + .class_size = sizeof(X86CPUClass), + .class_init = x86_cpu_common_class_init, + }, { + .name = X86_CPU_TYPE_NAME("base"), + .parent = TYPE_X86_CPU, + .class_init = x86_cpu_base_class_init, + }, { + .name = X86_CPU_TYPE_NAME("max"), + .parent = TYPE_X86_CPU, + .instance_init = max_x86_cpu_initfn, + .class_init = max_x86_cpu_class_init, + } }; +DEFINE_TYPES(x86_cpu_types) + static void x86_cpu_register_types(void) { int i; - type_register_static(&x86_cpu_type_info); for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { x86_register_cpudef_types(&builtin_x86_defs[i]); } - type_register_static(&max_x86_cpu_type_info); - type_register_static(&x86_base_cpu_type_info); } type_init(x86_cpu_register_types)