| Message ID | 20231009172129.43568-3-sebastian.reichel@collabora.com |
|---|---|
| State | New |
| Headers | show |
| Series | RK3588 USB3 host controller support | expand |
On Mon, Oct 09, 2023, Sebastian Reichel wrote: > On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and > requires two extra clocks to be enabled. Without these extra clocks > hot-plugging USB devices is broken. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++ > drivers/usb/dwc3/core.h | 4 ++++ > 2 files changed, 30 insertions(+) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 9c6bf054f15d..fc60d5f564dd 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -817,8 +817,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc) > if (ret) > goto disable_ref_clk; > > + ret = clk_prepare_enable(dwc->utmi_clk); > + if (ret) > + goto disable_susp_clk; > + > + ret = clk_prepare_enable(dwc->pipe_clk); > + if (ret) > + goto disable_utmi_clk; > + > return 0; > > +disable_utmi_clk: > + clk_disable_unprepare(dwc->utmi_clk); > +disable_susp_clk: > + clk_disable_unprepare(dwc->susp_clk); > disable_ref_clk: > clk_disable_unprepare(dwc->ref_clk); > disable_bus_clk: > @@ -828,6 +840,8 @@ static int dwc3_clk_enable(struct dwc3 *dwc) > > static void dwc3_clk_disable(struct dwc3 *dwc) > { > + clk_disable_unprepare(dwc->pipe_clk); > + clk_disable_unprepare(dwc->utmi_clk); > clk_disable_unprepare(dwc->susp_clk); > clk_disable_unprepare(dwc->ref_clk); > clk_disable_unprepare(dwc->bus_clk); > @@ -1748,6 +1762,18 @@ static int dwc3_get_clocks(struct dwc3 *dwc) > } > } > Can we add an inline comment here to note that these clocks are RKxxxx specifics. Thanks, Thinh > + dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); > + if (IS_ERR(dwc->utmi_clk)) { > + return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), > + "could not get utmi clock\n"); > + } > + > + dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); > + if (IS_ERR(dwc->pipe_clk)) { > + return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), > + "could not get pipe clock\n"); > + } > + > return 0; > } > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index a69ac67d89fe..f5e6ae6e394e 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -991,6 +991,8 @@ struct dwc3_scratchpad_array { > * @bus_clk: clock for accessing the registers > * @ref_clk: reference clock > * @susp_clk: clock used when the SS phy is in low power (S3) state > + * @utmi_clk: clock used for USB2 PHY communication > + * @pipe_clk: clock used for USB3 PHY communication > * @reset: reset control > * @regs: base address for our registers > * @regs_size: address space size > @@ -1156,6 +1158,8 @@ struct dwc3 { > struct clk *bus_clk; > struct clk *ref_clk; > struct clk *susp_clk; > + struct clk *utmi_clk; > + struct clk *pipe_clk; > > struct reset_control *reset; > > -- > 2.42.0 >
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 9c6bf054f15d..fc60d5f564dd 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -817,8 +817,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc) if (ret) goto disable_ref_clk; + ret = clk_prepare_enable(dwc->utmi_clk); + if (ret) + goto disable_susp_clk; + + ret = clk_prepare_enable(dwc->pipe_clk); + if (ret) + goto disable_utmi_clk; + return 0; +disable_utmi_clk: + clk_disable_unprepare(dwc->utmi_clk); +disable_susp_clk: + clk_disable_unprepare(dwc->susp_clk); disable_ref_clk: clk_disable_unprepare(dwc->ref_clk); disable_bus_clk: @@ -828,6 +840,8 @@ static int dwc3_clk_enable(struct dwc3 *dwc) static void dwc3_clk_disable(struct dwc3 *dwc) { + clk_disable_unprepare(dwc->pipe_clk); + clk_disable_unprepare(dwc->utmi_clk); clk_disable_unprepare(dwc->susp_clk); clk_disable_unprepare(dwc->ref_clk); clk_disable_unprepare(dwc->bus_clk); @@ -1748,6 +1762,18 @@ static int dwc3_get_clocks(struct dwc3 *dwc) } } + dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); + if (IS_ERR(dwc->utmi_clk)) { + return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), + "could not get utmi clock\n"); + } + + dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); + if (IS_ERR(dwc->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), + "could not get pipe clock\n"); + } + return 0; } diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index a69ac67d89fe..f5e6ae6e394e 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -991,6 +991,8 @@ struct dwc3_scratchpad_array { * @bus_clk: clock for accessing the registers * @ref_clk: reference clock * @susp_clk: clock used when the SS phy is in low power (S3) state + * @utmi_clk: clock used for USB2 PHY communication + * @pipe_clk: clock used for USB3 PHY communication * @reset: reset control * @regs: base address for our registers * @regs_size: address space size @@ -1156,6 +1158,8 @@ struct dwc3 { struct clk *bus_clk; struct clk *ref_clk; struct clk *susp_clk; + struct clk *utmi_clk; + struct clk *pipe_clk; struct reset_control *reset;
On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and requires two extra clocks to be enabled. Without these extra clocks hot-plugging USB devices is broken. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> --- drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 4 ++++ 2 files changed, 30 insertions(+)