@@ -144,12 +144,10 @@ static const struct clk_parent_data disp_cc_parent_data_2[] = {
};
static const struct parent_map disp_cc_parent_map_3[] = {
- { P_BI_TCXO, 0 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
- { .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll1.clkr.hw },
};
@@ -166,13 +164,11 @@ static const struct clk_parent_data disp_cc_parent_data_4[] = {
};
static const struct parent_map disp_cc_parent_map_5[] = {
- { P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
- { .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
};
@@ -219,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_shared_ops,
+ .ops = &clk_rcg2_parked_ops,
},
};
@@ -565,7 +561,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_shared_ops,
+ .ops = &clk_rcg2_parked_ops,
},
};
@@ -617,7 +613,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_shared_ops,
+ .ops = &clk_rcg2_parked_ops,
},
};
Switch MDP, AHB and ROT clocks to the clk_rcg2_parked_ops so that the CCF can properly determine if the clock is enabled or disabled. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sm8250.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-)