| Message ID | 20231006045317.1056625-5-quic_devipriy@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Enable pwm support for IPQ5332 & IPQ9574 SoCs | expand |
On 06/10/2023 06:53, Devi Priya wrote: > Add PWM support in ipq5332. The PWM is in the TCSR area. Make tcsr > "simple-mfd" compatible, and add pwm as a child of &tcsr. > > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index d3fef2f80a81..7620f1ccd324 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -210,8 +210,21 @@ tcsr_mutex: hwlock@1905000 { }; tcsr: syscon@1937000 { - compatible = "qcom,tcsr-ipq5332", "syscon"; + compatible = "qcom,tcsr-ipq5332", "syscon", "simple-mfd"; reg = <0x01937000 0x21000>; + ranges = <0x0 0x01937000 0x21000>; + #address-cells = <1>; + #size-cells = <1>; + + pwm: pwm@a010 { + compatible = "qcom,ipq5332-pwm", "qcom,ipq6018-pwm"; + reg = <0xa010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <2>; + status = "disabled"; + }; }; sdhc: mmc@7804000 {
Add PWM support in ipq5332. The PWM is in the TCSR area. Make tcsr "simple-mfd" compatible, and add pwm as a child of &tcsr. Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)