| Message ID | 20231003120846.28626-3-quic_nsekar@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/6] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy | expand |
On 3.10.2023 14:08, Nitheesh Sekar wrote: > Add support for the PCIe controller on the Qualcomm > IPQ5108 SoC to the bindings. > > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > --- [...] > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-ipq5018 > + then: > + properties: > + clocks: > + minItems: 6 > + maxItems: 6 > + clock-names: > + items: > + - const: iface # PCIe to SysNOC BIU clock What's a BIU? Konrad
On 10/7/2023 5:55 AM, Konrad Dybcio wrote: > On 3.10.2023 14:08, Nitheesh Sekar wrote: >> Add support for the PCIe controller on the Qualcomm >> IPQ5108 SoC to the bindings. >> >> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >> --- > [...] > >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,pcie-ipq5018 >> + then: >> + properties: >> + clocks: >> + minItems: 6 >> + maxItems: 6 >> + clock-names: >> + items: >> + - const: iface # PCIe to SysNOC BIU clock > What's a BIU? > > Konrad It is Bus Interface Unit. Thanks, Nitheesh
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index eadba38171e1..72e24094ec7e 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -170,6 +171,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 then: @@ -332,6 +334,39 @@ allOf: - const: ahb # AHB reset - const: phy_ahb # PHY AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq5018 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_bridge # AXI bridge clock + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core sticky reset + - const: axi_m # AXI master reset + - const: axi_s # AXI slave reset + - const: ahb # AHB reset + - const: axi_m_sticky # AXI master sticky reset + - const: axi_s_sticky # AXI slave sticky reset + - if: properties: compatible: @@ -790,6 +825,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074
Add support for the PCIe controller on the Qualcomm IPQ5108 SoC to the bindings. Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> --- .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+)