Message ID | 20230927140123.5283-2-joey.gouly@arm.com |
---|---|
State | Superseded |
Headers | show
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Wed, 27 Sep 2023 14:01:34 +0000 Received: from e124191.cambridge.arm.com (10.1.197.45) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Wed, 27 Sep 2023 14:01:34 +0000 From: Joey Gouly <joey.gouly@arm.com> To: <linux-arm-kernel@lists.infradead.org> CC: <nd@arm.com>, <akpm@linux-foundation.org>, <aneesh.kumar@linux.ibm.com>, <catalin.marinas@arm.com>, <dave.hansen@linux.intel.com>, <joey.gouly@arm.com>, <maz@kernel.org>, <oliver.upton@linux.dev>, <shuah@kernel.org>, <will@kernel.org>, <kvmarm@lists.linux.dev>, <linux-fsdevel@vger.kernel.org>, <linux-mm@kvack.org>, <linux-kselftest@vger.kernel.org> Subject: [PATCH v1 01/20] arm64/sysreg: add system register POR_EL{0,1} Date: Wed, 27 Sep 2023 15:01:04 +0100 Message-ID: <20230927140123.5283-2-joey.gouly@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230927140123.5283-1-joey.gouly@arm.com> References: <20230927140123.5283-1-joey.gouly@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT030:EE_|GV2PR08MB8511:EE_|DBAEUR03FT012:EE_|VE1PR08MB5712:EE_ X-MS-Office365-Filtering-Correlation-Id: fd5845d4-e12d-43f9-468a-08dbbf63874b x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Series |
Permission Overlay Extension
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expand
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On Wed, Sep 27, 2023 at 03:01:04PM +0100, Joey Gouly wrote: > Add POR_EL{0,1} according to DDI0601 2023-03. Reviewed-by: Mark Brown <broonie@kernel.org>
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 38296579a4fd..cc2d61fd45c3 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -994,6 +994,19 @@ #define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4)) +/* + * Permission Overlay Extension (POE) permission encodings. + */ +#define POE_NONE UL(0x0) +#define POE_R UL(0x1) +#define POE_X UL(0x2) +#define POE_RX UL(0x3) +#define POE_W UL(0x4) +#define POE_RW UL(0x5) +#define POE_XW UL(0x6) +#define POE_RXW UL(0x7) +#define POE_MASK UL(0xf) + #define ARM64_FEATURE_FIELD_BITS 4 /* Defined for compatibility only, do not add new users. */ diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 76ce150e7347..20f7dd25c221 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2504,6 +2504,14 @@ Sysreg PIR_EL2 3 4 10 2 3 Fields PIRx_ELx EndSysreg +Sysreg POR_EL0 3 3 10 2 4 +Fields PIRx_ELx +EndSysreg + +Sysreg POR_EL1 3 0 10 2 4 +Fields PIRx_ELx +EndSysreg + Sysreg LORSA_EL1 3 0 10 4 0 Res0 63:52 Field 51:16 SA
Add POR_EL{0,1} according to DDI0601 2023-03. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- arch/arm64/include/asm/sysreg.h | 13 +++++++++++++ arch/arm64/tools/sysreg | 8 ++++++++ 2 files changed, 21 insertions(+)