diff mbox series

[RFC,v2,net-next,11/15] net: phylink: support the 25GBase-KR-S and 25GBase-CR-S link modes too

Message ID 20230923134904.3627402-12-vladimir.oltean@nxp.com
State New
Headers show
Series Add C72/C73 copper backplane support for LX2160 | expand

Commit Message

Vladimir Oltean Sept. 23, 2023, 1:49 p.m. UTC 
Treat the newly introduced subsets of 25GBase-KR and 25GBase-CR the same
way as the fully-featured link modes. The difference only consists in
RS-FEC support.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v1->v2: patch is new

 drivers/net/phy/phylink.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Russell King (Oracle) Oct. 3, 2023, 11:31 a.m. UTC | #1 
On Sat, Sep 23, 2023 at 04:49:00PM +0300, Vladimir Oltean wrote:
> Treat the newly introduced subsets of 25GBase-KR and 25GBase-CR the same
> way as the fully-featured link modes. The difference only consists in
> RS-FEC support.

As mentioned in the patch adding these new linkmodes, I wonder whether
this should be part of that patch. Is there a reason to keep it
separate?
Vladimir Oltean Oct. 3, 2023, 4:24 p.m. UTC | #2 
Hi Russell,

On Tue, Oct 03, 2023 at 12:31:46PM +0100, Russell King (Oracle) wrote:
> On Sat, Sep 23, 2023 at 04:49:00PM +0300, Vladimir Oltean wrote:
> > Treat the newly introduced subsets of 25GBase-KR and 25GBase-CR the same
> > way as the fully-featured link modes. The difference only consists in
> > RS-FEC support.
> 
> As mentioned in the patch adding these new linkmodes, I wonder whether
> this should be part of that patch. Is there a reason to keep it
> separate?

I can squash this into the other CR-S/KR-S patch.
diff mbox series

Patch

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 6415c7b91053..157984dd81de 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -321,6 +321,8 @@  void phylink_caps_to_linkmodes(unsigned long *linkmodes, unsigned long caps)
 	if (caps & MAC_25000FD) {
 		__set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, linkmodes);
 		__set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, linkmodes);
+		__set_bit(ETHTOOL_LINK_MODE_25000baseCR_S_Full_BIT, linkmodes);
+		__set_bit(ETHTOOL_LINK_MODE_25000baseKR_S_Full_BIT, linkmodes);
 		__set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, linkmodes);
 	}
 
@@ -919,6 +921,8 @@  static int phylink_parse_mode(struct phylink *pl,
 		case PHY_INTERFACE_MODE_25GBASER:
 			phylink_set(pl->supported, 25000baseCR_Full);
 			phylink_set(pl->supported, 25000baseKR_Full);
+			phylink_set(pl->supported, 25000baseCR_S_Full);
+			phylink_set(pl->supported, 25000baseKR_S_Full);
 			phylink_set(pl->supported, 25000baseSR_Full);
 			fallthrough;
 		case PHY_INTERFACE_MODE_USXGMII:
@@ -948,6 +952,8 @@  static int phylink_parse_mode(struct phylink *pl,
 		case PHY_INTERFACE_MODE_XLGMII:
 			phylink_set(pl->supported, 25000baseCR_Full);
 			phylink_set(pl->supported, 25000baseKR_Full);
+			phylink_set(pl->supported, 25000baseCR_S_Full);
+			phylink_set(pl->supported, 25000baseKR_S_Full);
 			phylink_set(pl->supported, 25000baseSR_Full);
 			phylink_set(pl->supported, 40000baseKR4_Full);
 			phylink_set(pl->supported, 40000baseCR4_Full);