@@ -734,16 +734,26 @@ clk: clock-controller@30380000 {
<&clk IMX8MP_CLK_A53_CORE>,
<&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_NOC_IO>,
- <&clk IMX8MP_CLK_GIC>;
+ <&clk IMX8MP_CLK_GIC>,
+ <&clk IMX8MP_CLK_AUDIO_AHB>,
+ <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
+ <&clk IMX8MP_AUDIO_PLL1>,
+ <&clk IMX8MP_AUDIO_PLL2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_ARM_PLL_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL2_500M>;
+ <&clk IMX8MP_SYS_PLL2_500M>,
+ <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <0>, <0>,
<1000000000>,
<800000000>,
- <500000000>;
+ <500000000>,
+ <400000000>,
+ <800000000>,
+ <393216000>,
+ <361267200>;
};
src: reset-controller@30390000 {
Assign parent clock for audio AHB and AXI clocks, and assign clock rate for audio PLL1 and PLL2. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)