| Message ID | 20230913-gpll_cleanup-v2-3-c8ceb1a37680@quicinc.com |
|---|---|
| State | Accepted |
| Commit | 01a5e4c6731ab6b4b74822661d296f8893fc1230 |
| Headers | show |
| Series | [v2,01/11] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks | expand |
diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 19dc2b71cacf..2a3c0659b700 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -128,7 +128,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -143,7 +142,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -158,7 +156,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, };
GPLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> ---- Changes in V2: - New patch --- drivers/clk/qcom/gcc-ipq5018.c | 3 --- 1 file changed, 3 deletions(-)