Message ID | 20230910125726.1243652-1-festevam@gmail.com |
---|---|
State | Superseded |
Headers | show |
Series | [v2,1/2] arm64: dts: imx93: Add the TMU interrupt | expand |
Hi Krzysztof, On Mon, Sep 11, 2023 at 3:14 AM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 10/09/2023 14:57, Fabio Estevam wrote: > > From: Fabio Estevam <festevam@denx.de> > > > > imx93 has a maximum of seven entries for fsl,tmu-range. > > > > Then qoriq should have it constrained to 4 entries. I just noticed that fsl-lx2160a.dtsi is also has a tmu compatible with two entries. Would it be OK to represent it like this? --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml @@ -33,7 +33,8 @@ properties: description: | The values to be programmed into TTRnCR, as specified by the SoC reference manual. The first cell is TTR0CR, the second is TTR1CR, etc. - maxItems: 4 + minItems: 2 + maxItems: 7
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 6f85a05ee7e1..5d36b7a5bbd5 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -385,6 +385,7 @@ anatop: anatop@44480000 { tmu: tmu@44482000 { compatible = "fsl,qoriq-tmu"; reg = <0x44482000 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_TMC_GATE>; little-endian; fsl,tmu-range = <0x800000da 0x800000e9