| Message ID | 20230906184211.1857585-1-l.stach@pengutronix.de |
|---|---|
| State | Accepted |
| Commit | d0f4b70eb9a9ed05a37d963655698906cd4dac9a |
| Headers | show |
| Series | [v3,1/2] dt-bindings: phy: add binding for the i.MX8MP HDMI PHY | expand |
On 06.09.23 20:42, Lucas Stach wrote: > This adds the driver for the Samsung HDMI PHY found on the > i.MX8MP SoC. Based on downstream implementation from > Sandor Yu <Sandor.yu@nxp.com>. > > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> (v2) > Tested-by: Richard Leitner <richard.leitner@skidata.com> (v2) > Co-developed-by: Marco Felsch <m.felsch@pengutronix.de> > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > v3: > - use GENMASK/FIELD_PREP > - lowercase hex values > - correct coding style > v2: > - use DEFINE_RUNTIME_DEV_PM_OPS Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MP
Hi Lucas, [+Cc: Sandor] On Wed, 6 Sep 2023 20:42:11 +0200 Lucas Stach <l.stach@pengutronix.de> wrote: > This adds the driver for the Samsung HDMI PHY found on the > i.MX8MP SoC. Based on downstream implementation from > Sandor Yu <Sandor.yu@nxp.com>. > > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> (v2) Also for v3: [On custom board based on MSC SM2S-IMX8PLUS SMARC module] Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> I have a few notes however, see below. > +#define PHY_REG_14 0x38 > +#define REG14_TOL_MASK GENMASK(7, 4) > +#define REG14_RP_CODE_MASK GENMASK(2, 1) According to the latest reference manual currently available on the NXP website (Rev. 1, 06/2021), this should be GENMASK(3, 1). This is somewhat nitpicking as the only possible value documented is 2. But let's continue... > +#define PHY_REG_33 0x84 > +#define REG33_MODE_SET_DONE BIT(7) > +#define REG33_FIX_DA BIT(1) Here the reference manual is very different: MODE_SET_DONE BIT(4) TX_INV2 BIT(3) TX_INV1 BIT(2) TX_INV0 BIT(1) MON_RXD BIT(0) bits 7-5 are reserved ...which is strange: in the code you are always writing 0 in bit 4, which according to the docs means MODE_SET_DONE is always "Assert forced global reset". Thus I guess your definitions come from the downstream driver which, as it sadly happens, is more authoritative than the docs. :-/ Sandor, can you confirm this, or provide any clarifications? Otherwise LGTM. Luca
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml new file mode 100644 index 000000000000..61ffdc4d5792 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP HDMI PHY binding + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +description: + The HDMI PHY in the i.MX8MP SoC is implemented in 14nm technology and + is based on Samsung IP. + +properties: + compatible: + enum: + - fsl,imx8mp-hdmi-phy + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: apb + - const: ref + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - "#phy-cells" + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/power/imx8mp-power.h> + + phy@32fdff00 { + compatible = "fsl,imx8mp-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells = <0>; + #phy-cells = <0>; + };