@@ -230,6 +230,15 @@ blsp1_uart1: serial@f991d000 {
status = "disabled";
};
+ blsp1_uart2: serial@f991e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991e000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
blsp1_uart3: serial@f991f000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991f000 0x1000>;
@@ -313,6 +322,19 @@ blsp1_i2c5: i2c@f9927000 {
#size-cells = <0>;
};
+ blsp1_i2c6: i2c@f9928000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9928000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c6_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
cci: cci@fda0c000 {
compatible = "qcom,msm8226-cci";
#address-cells = <1>;
@@ -460,6 +482,13 @@ blsp1_i2c5_pins: blsp1-i2c5-state {
bias-disable;
};
+ blsp1_i2c6_pins: blsp1-i2c6-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cci_default: cci-default-state {
pins = "gpio29", "gpio30";
function = "cci_i2c0";
Add more busses found on msm8226 SoC. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)