@@ -61,13 +61,13 @@ enum AHCIHostReg {
AHCI_HOST_REG_CTL = 1, /* GHC: global host control */
AHCI_HOST_REG_IRQ_STAT = 2, /* IS: interrupt status */
AHCI_HOST_REG_PORTS_IMPL = 3, /* PI: bitmap of implemented ports */
- AHCI_HOST_REG_VERSION = 4, /* VS: AHCI spec. version compliancy */
+ AHCI_HOST_REG_VERSION = 4, /* VS: AHCI spec. version compliance */
AHCI_HOST_REG_CCC_CTL = 5, /* CCC_CTL: CCC Control */
AHCI_HOST_REG_CCC_PORTS = 6, /* CCC_PORTS: CCC Ports */
AHCI_HOST_REG_EM_LOC = 7, /* EM_LOC: Enclosure Mgmt Location */
AHCI_HOST_REG_EM_CTL = 8, /* EM_CTL: Enclosure Mgmt Control */
AHCI_HOST_REG_CAP2 = 9, /* CAP2: host capabilities, extended */
- AHCI_HOST_REG_BOHC = 10, /* BOHC: firmare/os handoff ctrl & status */
+ AHCI_HOST_REG_BOHC = 10, /* BOHC: firmware/os handoff ctrl & status */
AHCI_HOST_REG__COUNT = 11
};
@@ -257,7 +257,7 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
if (d->secondary) {
- /* XXX: if not enabled, really disable the seconday IDE controller */
+ /* XXX: if not enabled, really disable the secondary IDE controller */
pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
}
@@ -1698,7 +1698,7 @@ static bool cmd_set_features(IDEState *s, uint8_t cmd)
put_le16(identify_data + 63, 0x07);
put_le16(identify_data + 88, 0x3f);
break;
- case 0x02: /* sigle word dma mode*/
+ case 0x02: /* single word dma mode */
put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
put_le16(identify_data + 63, 0x07);
put_le16(identify_data + 88, 0x3f);