@@ -590,6 +590,7 @@ static const struct irq_chip amd_gpio_irqchip = {
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
+#define GPIO0_LESS_TIME (BIT(GPIO0_LESS_2_OFF) | BIT(GPIO0_LESS_10_OFF))
#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
@@ -610,6 +611,14 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ /* check GPIO0 specifically for Less2 and Less10 */
+ regval = readl(gpio_dev->base);
+ if (regval & GPIO0_LESS_TIME) {
+ pm_pr_dbg("GPIO0 was pressed for less than %d seconds\n",
+ regval & BIT(GPIO0_LESS_10_OFF) ? 10 : 2);
+ writel(regval | BIT(INTERRUPT_STS_OFF), gpio_dev->base);
+ }
+
/* Bit 0-45 contain the relevant status bits */
status &= (1ULL << 46) - 1;
regs = gpio_dev->base;
@@ -45,6 +45,8 @@
#define WAKECNTRL_Z_OFF 27
#define INTERRUPT_STS_OFF 28
#define WAKE_STS_OFF 29
+#define GPIO0_LESS_2_OFF 30
+#define GPIO0_LESS_10_OFF 31
#define DB_TMR_OUT_MASK 0xFUL
#define DB_CNTRl_MASK 0x3UL
On systems that don't program GPIO0 through _AEI may still control the power button via this GPIO. When the GPIO master controller register has bit 15 configured for `EnWinBlueBtn` this will cause GPIO 0 to behave differently. If the user presses the button for less than 2 seconds or less than 10 seconds then it is expected that interrupt status must be cleared by the GPIO driver. Reported-by: Luca Pigliacampo <lucapgl2001@gmail.com> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217833 Fixes: a855724dc08b ("pinctrl: amd: Fix mistake in handling clearing pins at startup") Link: https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/programmer-references/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf p948 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> --- drivers/pinctrl/pinctrl-amd.c | 9 +++++++++ drivers/pinctrl/pinctrl-amd.h | 2 ++ 2 files changed, 11 insertions(+)