diff mbox series

riscv: dts: allwinner: d1: Add PMU event node

Message ID IA1PR20MB495310F06009AA884D0612A1BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com
State Superseded
Headers show
Series riscv: dts: allwinner: d1: Add PMU event node | expand

Commit Message

Inochi Amaoto Aug. 26, 2023, 8:38 a.m. UTC 
D1 has several pmu events supported by opensbi.
These events can be used by perf for profiling.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 8275630af977..d9031ccdec89 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -72,5 +72,45 @@  plic: interrupt-controller@10000000 {
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 		};
+
+		pmu {
+			compatible = "riscv,pmu";
+			riscv,event-to-mhpmcounters =
+				<0x00003 0x00003 0x00000008>,
+				<0x00004 0x00004 0x00000010>,
+				<0x00005 0x00005 0x00000200>,
+				<0x00006 0x00006 0x00000100>,
+				<0x10000 0x10000 0x00004000>,
+				<0x10001 0x10001 0x00008000>,
+				<0x10002 0x10002 0x00010000>,
+				<0x10003 0x10003 0x00020000>,
+				<0x10019 0x10019 0x00000040>,
+				<0x10021 0x10021 0x00000020>;
+			riscv,event-to-mhpmevent =
+				<0x00003 0x00000000 0x00000001>,
+				<0x00004 0x00000000 0x00000002>,
+				<0x00005 0x00000000 0x00000007>,
+				<0x00006 0x00000000 0x00000006>,
+				<0x0000a 0x00000000 0x0000000b>,
+				<0x10000 0x00000000 0x0000000c>,
+				<0x10001 0x00000000 0x0000000d>,
+				<0x10002 0x00000000 0x0000000e>,
+				<0x10003 0x00000000 0x0000000f>,
+				<0x10019 0x00000000 0x00000004>,
+				<0x10021 0x00000000 0x00000003>;
+			riscv,raw-event-to-mhpmcounters =
+				<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
+				<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
+				<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
+				<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
+				<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
+				<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
+				<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
+				<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
+				<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
+				<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
+				<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
+				<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
+		};
 	};
 };