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[01/10] phy: xgene: rename "enum phy_mode" to "enum xgene_phy_mode"

Message ID 1467696237-27831-2-git-send-email-kishon@ti.com
State Accepted
Commit 65048f4dd9fae7335b48ab23a879119c0e7fa105
Headers show

Commit Message

Kishon Vijay Abraham I July 5, 2016, 5:23 a.m. UTC 
No functional change. Rename "enum phy_mode" to
"enum xgene_phy_mode" in xgene phy driver in
preparation for adding set_mode callback in
phy core.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

Reviewed-by: Loc Ho <lho@apm.com>

---
 drivers/phy/phy-xgene.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
1.7.9.5
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Patch

diff --git a/drivers/phy/phy-xgene.c b/drivers/phy/phy-xgene.c
index 385362e..ae266e0 100644
--- a/drivers/phy/phy-xgene.c
+++ b/drivers/phy/phy-xgene.c
@@ -518,7 +518,7 @@  enum clk_type_t {
 	CLK_INT_SING = 2,	/* Internal single ended */
 };
 
-enum phy_mode {
+enum xgene_phy_mode {
 	MODE_SATA	= 0,	/* List them for simple reference */
 	MODE_SGMII	= 1,
 	MODE_PCIE	= 2,
@@ -542,7 +542,7 @@  struct xgene_sata_override_param {
 struct xgene_phy_ctx {
 	struct device *dev;
 	struct phy *phy;
-	enum phy_mode mode;		/* Mode of operation */
+	enum xgene_phy_mode mode;		/* Mode of operation */
 	enum clk_type_t clk_type;	/* Input clock selection */
 	void __iomem *sds_base;		/* PHY CSR base addr */
 	struct clk *clk;		/* Optional clock */