| Message ID | 20230811-upstream_csi-v9-7-8943f7a68a81@ti.com |
|---|---|
| State | New |
| Headers | show |
| Series | CSI2RX support on J721E and AM62 | expand |
On 11/08/2023 13:47, Jai Luthra wrote: > From: Pratyush Yadav <p.yadav@ti.com> > > This resets the stream state machines and FIFOs, giving them a clean > slate. On J721E if the streams are not reset before starting the > capture, the captured frame gets wrapped around vertically on every run > after the first. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Reviewed-by: Maxime Ripard <mripard@kernel.org> > Signed-off-by: Jai Luthra <j-luthra@ti.com> > --- > Changes from v8: > - Simplify reset sequence, minimizing delays > > drivers/media/platform/cadence/cdns-csi2rx.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c > index 933edec89520..b57e0c3b1944 100644 > --- a/drivers/media/platform/cadence/cdns-csi2rx.c > +++ b/drivers/media/platform/cadence/cdns-csi2rx.c > @@ -40,6 +40,7 @@ > #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) > > #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) > +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) > #define CSI2RX_STREAM_CTRL_START BIT(0) > > #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) > @@ -134,12 +135,23 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) > > static void csi2rx_reset(struct csi2rx_priv *csi2rx) > { > + unsigned int i; > + > + /* Reset module */ > writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, > csi2rx->base + CSI2RX_SOFT_RESET_REG); > + /* Reset individual streams. */ > + for (i = 0; i < csi2rx->max_streams; i++) { > + writel(CSI2RX_STREAM_CTRL_SOFT_RST, > + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); > + } > > - udelay(10); > + usleep_range(10, 20); > > + /* Clear resets */ > writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); > + for (i = 0; i < csi2rx->max_streams; i++) > + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); > } > > static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx) > Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Tomi
diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 933edec89520..b57e0c3b1944 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -40,6 +40,7 @@ #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) #define CSI2RX_STREAM_CTRL_START BIT(0) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) @@ -134,12 +135,23 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) static void csi2rx_reset(struct csi2rx_priv *csi2rx) { + unsigned int i; + + /* Reset module */ writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, csi2rx->base + CSI2RX_SOFT_RESET_REG); + /* Reset individual streams. */ + for (i = 0; i < csi2rx->max_streams; i++) { + writel(CSI2RX_STREAM_CTRL_SOFT_RST, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + } - udelay(10); + usleep_range(10, 20); + /* Clear resets */ writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); + for (i = 0; i < csi2rx->max_streams; i++) + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); } static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx)